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DESIGN OF ALU AND DUAL PORT SRAM CELLS FOR IMPLEMENTATION IN RISC BASED PROCESSING ELEMENTS

VAGHEESWAR, V. SATHYA
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069338283

Abstract Details

2003, MS, University of Cincinnati, Engineering : Electrical Engineering.
The importance and the need for photonic CMOS information processing systems has been well emphasized over the last decade due to the following advantages: massive parallelism/ high bandwidth communication cost of implementation of CMOS, reliability of the data that is transferred, reliability of the CMOS process. Previously, these photonic systems, also called “Smart Pixels” were available with the chips being designed and implemented as Application Specific Integrated Circuits (ASICs) rather than generically programmable microprocessors. The movement of data in a computer is unlike the movement of traffic in a city. The downtown which is the center of activity is the slowest with the speed increasing as we move away. In a computing system, the activity is the fastest near the core and it slows drastically as we move to the peripheral devices. The importance of optical interconnects are slowly getting the attention it needed as the current technology is not able to keep up with the insatiable need for high bandwidth communication of today and years to come. What is the point in getting the processors to perform in the tens of giga-hertz when the bus speeds are only in the hundreds of mega-hertz? The importance of optical interconnects comes into play at this juncture. Normally, the optical part gets into prominence as the medium of data transfer. In this research project, I am presenting the design of ALU and Dual port SRAM cells that formed part of a programmable architecture denoted CASPR-2 (Configurable Architecture for Smart Pixel Research) that fits into either ends of the optical medium, as processors of the transmitted optical signals.
Dr. Fred R. Beyette, Jr. (Advisor)
56 p.
ALU; Dual port; SRAM; RISC; processing elements

Recommended Citations

Citations

  • VAGHEESWAR, V. S. (2003). DESIGN OF ALU AND DUAL PORT SRAM CELLS FOR IMPLEMENTATION IN RISC BASED PROCESSING ELEMENTS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069338283

    APA Style (7th edition)

  • VAGHEESWAR, V. SATHYA. DESIGN OF ALU AND DUAL PORT SRAM CELLS FOR IMPLEMENTATION IN RISC BASED PROCESSING ELEMENTS. 2003. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069338283.

    MLA Style (8th edition)

  • VAGHEESWAR, V. SATHYA. "DESIGN OF ALU AND DUAL PORT SRAM CELLS FOR IMPLEMENTATION IN RISC BASED PROCESSING ELEMENTS." Master's thesis, University of Cincinnati, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069338283

    Chicago Manual of Style (17th edition)

ucin1069338283
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© 2003, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.