Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


ucin1085765670.pdf (556.06 KB)

ETD Abstract Container

Abstract Header

SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS

GHOSH, SWAROOP
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670

Abstract Details

2004, MS, University of Cincinnati, Engineering : Computer Engineering.
Recently, it has been observed that embedded cores in a high-speed SoC circuit have the problem of broken scan chains that cannot shift properly. Also, scan chain intermittent faults caused by holdtime violations and crosstalk noises are pervasive. In this research, an efficient method is proposed to identify the faulty scan chain(s) at the core level. That is, the core where the scan chain is defective can be identified, even if the scan chain is broken. The result can be used to tune up the fabrication process or to guide the fine-grained scan cell identification process. Here, weight-based m-out-of-n codes, which can generate a large number of codewords, with small hardware overhead and high fault detection capability are used to generate the scan chain diagnostic patterns for permanent and intermittent faults. An efficient codeword generation method is proposed to maximize the number of codewords, minimize the aliasing probabilities and test application cost. Aliasing probabilities are analyzed thoroughly for code sequences that are shifted to the scan chain in an overlapped manner. The idea of multiple m-out-of-n codes is also proposed to guarantee that sufficient number of codewords are generated to perturb the scan chains and the associated combinational circuits. A test pattern broadcast architecture is incorporated to support the proposed testing method. The complexity of control signal generation and scan chain test is greatly reduced by adopting this architecture. Further, by adding a test pattern alignment scheme, it is possible to share the control signals for all checkers and to support the broadcast architecture as well. Therefore, the hardware overhead of the test architecture is also reduced. Finally, a totally self-checking checker is designed to support the application of multiple weight-based codes. Simulation results demonstrate the feasibility of the proposed method as the aliasing probability is zero in almost every code sequence.
Dr. Wen-Ben Jone (Advisor)
65 p.
Scan chain testing; SoC circuits; weight-based codes; m-out-of-n codes; self-checking checkers; bidirectional and multi-directional aliasing analysis; broadcast architecture; intermittent faults

Recommended Citations

Citations

  • GHOSH, S. (2004). SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670

    APA Style (7th edition)

  • GHOSH, SWAROOP. SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS. 2004. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670.

    MLA Style (8th edition)

  • GHOSH, SWAROOP. "SCAN CHAIN FAULT IDENTIFICATION USING WEIGHT-BASED CODES FOR SoC CIRCUITS." Master's thesis, University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1085765670

    Chicago Manual of Style (17th edition)

ucin1085765670
962
© 2004, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.