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A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS

VIJAY, VIKAS

Abstract Details

2004, MS, University of Cincinnati, Engineering : Computer Engineering.
This thesis presents automated techniques for synthesis of high performance RF circuits. The top-down methodology developed encompasses all stages of RF design from circuit sizing, layout generation to parasitic extraction and performance analysis. The objective of this methodology is to minimize the design time and generate efficient, correct and re-usable design solutions. In the proposed methodology, given a circuit netlist and a set of performance goals, a ready-to-tapeout layout is generated which meets the specified performance constraints. A sizing tool is integrated to perform design space exploration. A parameterized layout generator generates the layout based on the input sizes. An RF-Performance Analysis system (PAS-RF) comprising of a set of C++ functions is also developed for measuring the performance of the RF circuit. The proposed methodology is successfully tested by synthesizing variants of RF receiver circuits (LNA, Mixers, VCO etc.) for different performance criterion.
Dr. Ranga Vemuri (Advisor)
176 p.

Recommended Citations

Citations

  • VIJAY, V. (2004). A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

    APA Style (7th edition)

  • VIJAY, VIKAS. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. 2004. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

    MLA Style (8th edition)

  • VIJAY, VIKAS. "A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS." Master's thesis, University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

    Chicago Manual of Style (17th edition)