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IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE

RAJAGOPALAN, JAYANTHI
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100886361

Abstract Details

2004, MS, University of Cincinnati, Engineering : Computer Engineering.
Today's complex reconfigurable computing applications demand a higher adaptability and flexibility in FPGAs. All existing FPGAs focus on synchronous designs and have dedicated clock signals, which limit their performance and optimization. Considering the many potential benefits of the asynchronous or self-timed timing paradigms, the DRAPL (Dynamically Reconfigurable Asynchronous Programmable Logic) architecture is developed. DRAPL array is a flexible reconfigurable hardware platform and adopts Globally Asynchronous Locally Synchronous (GALS) design style. The design consists of Timing regions that operate independently under locally generated clocks and selectively communicate with each other through handshaking asynchronous interfaces. Each Timing region also gains access to the central reconfiguration controller and hence gets the ability to reconfigure other Timing Regions. These features add more flexibility to DRAPL compared to the existing FPGA architectures since (i) Function cores implemented on different Timing regions can be optimized separately, which reduce the time and efforts of optimization in a big system. (ii) Each function core can modify itself or others at runtime based on the specific application requirement. This thesis implements the key modules of the DRAPL Architecture developed by Xin Jia and Dr. Ranga Vemuri. Layouts of the Timing and Logic array are devised and the functioning, especially, the Handshaking communication between the Timing Regions is verified with the help of the simulation results obtained. The performance of the DRAPL architecture is determined with the help of the performance parameters including Power, Area and Delay.
Dr. Ranga Vemuri (Advisor)
146 p.
Asynchronous; FPGA; Self-timing; Handshaking communication; Timing Cell; Timing Region; Programmable Logic

Recommended Citations

Citations

  • RAJAGOPALAN, J. (2004). IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100886361

    APA Style (7th edition)

  • RAJAGOPALAN, JAYANTHI. IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE. 2004. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100886361.

    MLA Style (8th edition)

  • RAJAGOPALAN, JAYANTHI. "IMPLEMENTATION OF A DYNAMICALLY RECONFIGURABLE ASYNCHRONOUS PROGRAMMABLE LOGIC (DRAPL) ARCHITECTURE." Master's thesis, University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100886361

    Chicago Manual of Style (17th edition)

ucin1100886361
902
© 2004, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.