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AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS

RANJAN, MUKESH

Abstract Details

2005, PhD, University of Cincinnati, Engineering : Computer Science and Engineering.
A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of a fixed topology, while being subjected to a set of performance constraints. Over the years, the terms sizing and synthesis have been used interchangeably, and have become synonymous in the analog domain. Mature tools for the synthesis of digital circuits are abundant, but the market for analog synthesis tools is still growing and very few commercial products exist. Several techniques have been developed in the past for analog synthesis, ranging from knowledge-based methods to techniques using numerical simulation. A frequently used technique involves an iterative stochastic search, which uses numerical simulations at every probable design point, in order to obtain the performance metrics. Expensive computations and parasitics unawareness of this traditional method necessitates a scheme which can produce fast layout aware designs. In this dissertation a new synthesis methodology, which uses parameterized layout generators and symbolic performance models (SPMs) inside the synthesis loop, has been developed to overcome the deficiencies of the previous circuit sizing method. This layout-inclusive (layout-in-loop) approach uses efficient parameterized procedural layout generators, obtained using the module specification language (MSL) system, for speedy layout instantiation. Fast performance estimation is achieved by using pre-compiled SPMs, which are symbolic representation of circuit performances, obtained using symbolic analysis. The transfer functions of SPMs are stored as efficient symbolic graphs called element-coefficient diagrams (ECDs). Techniques to include layout geometry effects in the SPMs have also been developed. This method is used for the synthesis of op-amps and filters. The method proposed above for analog circuits is then applied to the synthesis of an RF low-noise amplifier (LNA). This method also uses symbolic performance models (SPMs), and parameterized layout generator along with high-frequency extraction techniques in the synthesis loop. SPMs for noise figure and distortion parameters are developed using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled ECDs. Full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. Further in the dissertation, efforts are made to overcome the shortcomings of the proposed method. The first limitation is the size of circuits that can be synthesized. It arises because of the limit on the size of ECD-code that can be compiled by a standard GNU C++ compiler. To overcome this bottleneck, a new comprehensive method and framework for exact symbolic analysis of large analog circuits is developed. The method is based on the concepts of hierarchical circuit decomposition, subcircuit symbolic analysis and transfer function synthesis. Node tearing methods have been used for decomposition and element-coefficient diagrams (ECD) based method is used for symbolic analysis of subcircuits. One of the key contributions of this work is a generalized methodology for transfer function synthesis, encompassing all interconnection templates for any two subcircuits. The method leads to the development of an easily automatable and efficient algorithm for generation of symbolic transfer function of large circuits. The hierarchical technique, developed in this work, is then used for layout-inclusive synthesis of large analog circuits. Techniques have been developed to generate the list and interconnection of subcircuits which undergo hierarchical symbolic analysis. A circuit is decomposed into common building blocks of analog circuits, for which netlists are obtained by an extraction of corresponding layout modules. The interconnection parasitics may or may not exist in the module netlists and therefore they may form subcircuits of their own. The other shortcoming of this work is that of time during performance estimation is spent on operating point analysis using SPICE, a numerical simulator. To remove this dependence on numerical simulation and further speedup synthesis, we have developed a modified gm/ID method and used it for synthesis of analog circuits. EKV MOSFET model equations for all small-signal parameters have been extracted, and the conditions for a transistor to be in saturation, have been derived.
Dr. Ranga Vemuri (Advisor)
159 p.

Recommended Citations

Citations

  • RANJAN, M. (2005). AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

    APA Style (7th edition)

  • RANJAN, MUKESH. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. 2005. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

    MLA Style (8th edition)

  • RANJAN, MUKESH. "AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS." Doctoral dissertation, University of Cincinnati, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

    Chicago Manual of Style (17th edition)