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ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS

AGARWAL, ANURADHA
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

Abstract Details

2005, PhD, University of Cincinnati, Engineering : Computer Science and Engineering.
With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a significant momentum. With this need,comes the responsibility of bringing about mature computer-aided design (CAD) techniques to handle the complexity of designing such systems. Although mature commercial techniques exist for designing the digital components in a system, design automation for the irreplaceable analog and radio-frequency (RF) circuits in a system remains incipient. Circuit sizing is one of the most important and challenging constituents of any analog design process. Given a set of high-level specifications and a circuit topology, sizing aims to determine the device dimensions and biasing information in order to meet the desired specifications. In this dissertation, we address two major problems ailing the sizing process. One of the most important challenges in analog synthesis is to design a circuit which meets the input specifications at the post-layout stage. The other problem we seek to address in this dissertation is the enormous time spent in sizing due to the overhead of running thousands of simulations for performance estimation. Analog and RF circuits are extremely sensitive to layout parasitics. This extreme dependence of the behavior of analog circuits, on layout-induced parasitics, is responsible for several silicon runs before a functional chip can be designed. We propose two techniques to introduce layout awareness during circuit sizing. The first approach is based on developing fast and accurate models of the layout parasitics. The parasitic capacitance models are used inside a circuit sizing framework to estimate the layout parasitics and account for them in the performance evaluation process. This approach relies on procedural layout generators (PLGs) for developing the parasitic models. The second approach proposed for layout-aware design draws a similarity between layout parasitics and process variables in a yield optimization problem. A two-step approach is proposed for identifying the worst case parasitic corners and for sizing in presence of these parasitics. A parasitic robust design is sought for which passes the post-layout validation test. Circuit sizing primarily comprises of two components: a search engine and a performance estimator. Stochastic combinatorial optimization techniques are used for exploring the design space. For each candidate design explored by the search engine, the circuit performance is estimated. Typically, the performance estimation time dominates the overall synthesis time. Most commercial approaches deploy a simulator-in-loop approach to the sizing problem due to the high accuracy desired from the estimation process. We propose two techniques for replacing the simulator with accurate and efficient performance models. Since the performance models allow a very quick evaluation of the circuit performance, their use helps in drastically reducing the time complexity of sizing. Unlike the existing macro-model driven sizing techniques, the proposed approaches guarantee to obtain accurate simulator validated design solutions. We propose a unified system which aims to resolve both the problems of computational complexity of performance estimation and performance closure at the layout stage in the same flow. The proposed system combines the ideas of parasitic modeling, design optimization in presence of worst case parasitics corners and performance macromodeling put forth in this dissertation to create high quality designs efficiently.
Dr. Ranga Vemuri (Advisor)
152 p.
Analog; Radio-frequency; Circuit Synthesis; Layout Parasitics; Performance Modeling; Parasitic Estimation and Modeling; Layout-Aware Synthesis; Circuit sizing; Parasitic Corners; Yield Optimization; Parasitic Capacitances; Dynamic Performance Macromodel

Recommended Citations

Citations

  • AGARWAL, A. (2005). ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

    APA Style (7th edition)

  • AGARWAL, ANURADHA. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. 2005. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

    MLA Style (8th edition)

  • AGARWAL, ANURADHA. "ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS." Doctoral dissertation, University of Cincinnati, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

    Chicago Manual of Style (17th edition)

ucin1132259454
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© 2005, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.