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USING RUNTIME INFORMATION TO IMPROVE MEMORY SYSTEM PERFORMANCE

MIN, RUI
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1134043707

Abstract Details

2005, PhD, University of Cincinnati, Engineering : Computer Engineering.
In this dissertation, I present several high-performance and low-power architecture designs, which use memory reference information to optimize the memory behavior. More specifically, the TLB decoupling technique uses the runtime memory reference information collected at the TLB level to manipulate data locations on the L2 cache system, so that actively access memory regions will not be mapped to the same L2 cache partition. The Plot Cache hardware/software design collects memory traces as plots. The plots are analyzed and the information stored in the plots are used to optimize paging behavior in the OS. The selective way activation designs, use partial comparison information or previously generated location information to determine the location of the data. The references to the un-necessary regions are filtered out so as to save access power of caches. The location cache also reduces the average cache access latency. Experiment results from the proposed systems show very promising improvements in performance. The color-indexed, physically tagged cache strategy enables a direct-mapped cache to achieve hit ratios very close to or better than those of a two-way set associative cache. Moreover, the architecture does not increase cache access latency, which is a drawback of set associative caches. We show that our scheme can reduce the cache size by 50% without sacrificing performance. Simulation results based on NPB benchmarks show that the pattern-based page replacement strategy can drastically reduce the amount of page I/O traffic, and the prefetching mechanism hides up to 70% of page I/O latencies. The proposed schemes, when combined together with the page-clustering policy, can finally reduce the swapping overhead of conventional demand paging systems up to a magnitude of two. Finally, the power-aware architecture designs consumes 25-60% less power than a traditional set-associative cache and reduce the average cache access latency upto 25%.
Dr. Yiming Hu (Advisor)
97 p.
TLB; Cache; Virtual Memory; OS; Set Associativity

Recommended Citations

Citations

  • MIN, R. (2005). USING RUNTIME INFORMATION TO IMPROVE MEMORY SYSTEM PERFORMANCE [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1134043707

    APA Style (7th edition)

  • MIN, RUI. USING RUNTIME INFORMATION TO IMPROVE MEMORY SYSTEM PERFORMANCE. 2005. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1134043707.

    MLA Style (8th edition)

  • MIN, RUI. "USING RUNTIME INFORMATION TO IMPROVE MEMORY SYSTEM PERFORMANCE." Doctoral dissertation, University of Cincinnati, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1134043707

    Chicago Manual of Style (17th edition)

ucin1134043707
588
© 2004, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.