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PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs

HUANG, RENQIU
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

Abstract Details

2006, PhD, University of Cincinnati, Engineering : Computer Science and Engineering.
Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role. Synthesizing the application from concept and prototyping onto reconfigurable FPGAs has emerged as one of the main challenges in design automation area. A large number of new applications show the huge potentials of synthesis strategy and architecture development for FPGAs. The work presented in this dissertation deals with the synthesis and novel architecture of FPGAs. In particular, it tries to address physical aware high level synthesis (PAHLS) methodology to ensure the synthesis integrity for FPGAs. Motivated by the study of PAHLS, a hybrid interconnect structure is proposed to increase the performance and reconfigurability for FPGAs or FPGA-like reconfigurable platforms. We first present a performance-driven PAHLS where relational placement is combined with the macro generation strategy during high level synthesis. Second, we present an automated framework to integrate physical placement information into high-level synthesis that is believed to be the first on-line synthesis methodology for partially reconfigurable FPGAs. The presented synthesizer allocates the FPGA resources adaptively and is incremental in nature. The algorithm is designed to be linear in terms of the number of operations to ensure its on-line usage. We then present a transformation mechanism to extend the synthesis frontier to heterogeneous configurable architectures. We develop an automatic synthesis methodology which attacks both memory and logic assignments by interacting with behavioral synthesis. Next, we present a hybrid interconnect structure which takes advantages of both mesh and tree interconnect topologies. The presented architecture is investigated with a combinatorial analysis which examines the number of switches needed. Our evaluation demonstrates that the presented model has less switch accrued effects due to the introduction of tree networks. Finally we extend that hybrid interconnect structure to support multi-granular configuration. We also develop a fast evaluation tool to simulate on-line placement and routing effects by applying that interconnect on a run-time reconfigurable platform. The studies show the efficiency of the extended model in overcoming the fragmentation problem with a penalty of modest increase in the number of switches for the construction of that interconnect.
Dr. Ranga Vemuri (Advisor)
140 p.
Computer Science
High level synthesis; system synthesis; algorithm; architecture; performance; interconnect; analysis; evaluation

Recommended Citations

Citations

  • HUANG, R. (2006). PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

    APA Style (7th edition)

  • HUANG, RENQIU. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. 2006. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.

    MLA Style (8th edition)

  • HUANG, RENQIU. "PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs." Doctoral dissertation, University of Cincinnati, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

    Chicago Manual of Style (17th edition)

ucin1147616884
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© 2006, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.