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A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS

YAN, JIANPING
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

Abstract Details

2006, MS, University of Cincinnati, Engineering : Computer Engineering.
Current SRAM FPGAs have reached high gate densities which make them suitable for portable reconfigurable systems and data intensive applications. However, some challenges need to be faced to make this become a reality. First, due to a large number of transistors for field programmability and low utilization rate of FPGA resources, existing FPGAs are highly power hungry compared to ASICs. As chip technology progresses to 90 nm and below, this situation becomes worse and static current plays a major role in the total power. Second, the present column-based configuration structure is not flexible enough for applications with multiple reconfigurations. Unnecessary memory bits have to be configured if the layout of the module does not fully occupy the height of the device and, consequently, introduces wastage of time and energy. Third, the global clock distribution over the whole chip results in a very high power consumption. Even when some parts of the hardware resources are not used, the whole clock line must be switched at every clock cycle. Finally, current FPGAs can not support bus routing structure. The implementation of data intensive applications using traditional bit-based routing tracks will require more routing resource and produce higher power consumption. A lot of previous efforts have been made on FPGA power modeling and power reduction. In the work of power modeling and estimation for SRAM FPGAs, none of them has considered the impact of inrush current and configuration current, which can not be neglected for low-power applications that need multiple reconfigurations. For the previous power reduction architectures, some of them considered either one of dynamic power reduction or static power reduction. The other architectures such as dual-Vdd FPGA architecture considered both dynamic power and static power reduction. But their implementations produce significant area and configuration time overheads and the power management strategy is very inefficient since it is based on fine grained logic blocks or routing switches. The complex power management makes these architectures not practical for the real time applications that need multiple dynamic reconfigurations. This thesis proposes a battery-aware tiled FPGA architecture for data intensive computations. The architecture is globally coarse-grained in terms of FPGA tiles and locally fine-grained in terms of configurable logic blocks within each FPGA tile. The main feature of the architecture is that the power supply to each tile can be turned on/off depending on the computational requirements and system load. The static control strategy is fairly simple, which makes the area and configuration time overheads relatively small. The architecture adopts a two-level configuration structure, column-based programming and fully random access programming, which can efficiently reduce the configuration time and energy, while keeping the overheads of pin count and area relatively small. This combined configuration architecture enables the easy task relocation from one tile to another. The top level routing architecture between tiles is a combined bus-based and bit-based routing structure, which is very efficient for data intensive applications. A simulation platform is built with NetLogo to evaluate the proposed architecture. Besides dynamic and static currents, inrush and configuration currents are also considered. The static control function is implemented in the platform to reflect the main feature of the architecture which is the coarse-grained power supply control strategy. Experimental results on some randomly generated task graphs and a JPEG encoder show that: (1) tradeoff between execution time and power/battery usage can be achieved by using different number of tiles in the architecture; (2) significant savings in battery/energy cost can be achieved by using the static control function provided by the architecture; (3) by varying the architectural parameters of the tiled FPGA, more savings in battery/energy cost could be obtained.
Dr. Ranga Vemuri (Advisor)
70 p.
FPGA; Power Consumption; Architecture; Simulation

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Citations

  • YAN, J. (2006). A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

    APA Style (7th edition)

  • YAN, JIANPING. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. 2006. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839.

    MLA Style (8th edition)

  • YAN, JIANPING. "A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS." Master's thesis, University of Cincinnati, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

    Chicago Manual of Style (17th edition)

ucin1150126839
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© 2006, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.