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AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER

WANG, CHIH-KUAN

Abstract Details

2006, MS, University of Cincinnati, Engineering : Computer Engineering.
This thesis presents an iterative, crosstalk aware timing analyzer. Parameters such as slew rate, voltage supply, coupling capacitance, and load capacitance are shown to affect gate delays in coupling structures. The concept of relative signal arrival time and delay degradation curves is used to reduce pessimism in STA by Sasaki in [1]. This thesis extends the work of Sasaki to an iterative algorithm while also considering dual supply voltges. The algorithm uses empirical look up tables to model crosstalk noise. The tables, which include delays for three-line structures, are then mapped to any n-line structure. An initial solution is calculated in one pass. Subsequent passes iteratively improve the solution by modeling delays outside the three-line structure by changing the output loads of the outer lines in the three-line structure. This thesis proposes a iterative method of crosstalk aware timing analysis. The results obtained by this method match HSpice simulation results very well.
Dr. Wen-Ben Jone (Advisor)
112 p.

Recommended Citations

Citations

  • WANG, C.-K. (2006). AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235

    APA Style (7th edition)

  • WANG, CHIH-KUAN. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. 2006. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

    MLA Style (8th edition)

  • WANG, CHIH-KUAN. "AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER." Master's thesis, University of Cincinnati, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235

    Chicago Manual of Style (17th edition)