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ANALOG SIMULATION TIME REDUCTION BASED ON VARIABLE TOLERANCE RELAXATION

KUMAR, VINAYAK
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163019325

Abstract Details

2006, MS, University of Cincinnati, Engineering : Computer Engineering.
Circuit simulation, arguably the most used tool amongst the tools required for very large circuit design, provides the means to validate electrical circuits and also to perform behavioral analysis. As the size and the complexity of circuits are growing exponentially, simulation of the circuits is taking enormous amount of processing time. As a result, simulation time is becoming a major bottleneck in performance. The purpose of this research work is to implement an algorithm to reduce simulation time of circuits under certain constraints. The algorithm is called the Analog Simulation Time Reduction using Variable Tolerance Relaxation (VTR) and can be particularly useful to a circuit designer who aspires to achieve desired simulation accuracy of only a part of a large analog circuit (rather than the entire). The main purpose of this algorithm is to maintain the desired accuracies of the variables, either node voltages or branch currents, in this small part of the circuit, while reducing the simulation time of the circuit. To achieve this objective, the algorithm uses a tolerance relaxation technique applied to all variables not of interest of designer while assuring the accuracy of all variables in interest to the designer. Variable- sensitivity analysis is automatically performed to determine the relaxed tolerances for uninteresting variables while maintaining desired accuracies of variables of interest. The VTR algorithm is executed during the initial stage of the simulation so that rest of the simulation can be done with relaxed tolerances of the variables. In this study, circuits were restricted to passive and linear-active circuits only. The experiment results showed maximum simulation time improvements of twenty-five percent over a broad range of passive and linear active circuits ranging in size from 23 to 91 elements. In no case did simulation time increase.
Dr. Harold Carter (Advisor)
85 p.
Simulation; Tolerance relaxation; Simulation time reduction

Recommended Citations

Citations

  • KUMAR, V. (2006). ANALOG SIMULATION TIME REDUCTION BASED ON VARIABLE TOLERANCE RELAXATION [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163019325

    APA Style (7th edition)

  • KUMAR, VINAYAK. ANALOG SIMULATION TIME REDUCTION BASED ON VARIABLE TOLERANCE RELAXATION. 2006. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163019325.

    MLA Style (8th edition)

  • KUMAR, VINAYAK. "ANALOG SIMULATION TIME REDUCTION BASED ON VARIABLE TOLERANCE RELAXATION." Master's thesis, University of Cincinnati, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163019325

    Chicago Manual of Style (17th edition)

ucin1163019325
490
© 2006, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.