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GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE

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2007, PhD, University of Cincinnati, Engineering : Computer Engineering.
Conventional FPGAs, designed to implement synchronous circuits and systems, are facing some challenges. (1) The delays of the long interconnect wires can easily dominate all other delays and severely reduce the application clock rates. For example, the corner-to-corner interconnect delay of a xc2v8000 FPGA is about 14.9ns. A synchronous design using such an interconnection can run under the clock speed of no more than 67MHz. (2) A multitude of modules running at different clock frequencies are likely to be integrated on a single FPGA to form a single-chip solution since FPGAs have grown to sufficient sizes. Data communication between modules means to move data across different clock domains. Therefore, the data signals appear to be asynchronous in the new clock domain. Current FPGA architectures and CAD tools provide very few or even no support for asynchronous communications. Therefore, it is up to the designer to build reliable circuits for communications across clock domains, which is tedious and error-prone. (3) Clock distribution network is complicated and power consuming. (4) Dynamically partial reconfigurability is becoming crucial to FPGAs. But current FPGA support for dynamically partial reconfiguration is at best tedious since changing of one part might violate the global clock restriction in a monotonic clock realm. Introducing asynchronous concept into the FPGA architecture is a possible solution to the named challenges. Asynchronous designs provide average-case performance instead of the worst-case performance provided by the synchronous designs. In terms of interconnect delays, performance is dictated by the average of the interconnect delays rather than the worst-case delay. Hence use of long wires does not necessarily lead to a significant performance penalty. By adopting asynchronous design, FPGAs then an provide architectural supports for communications across different clock domains. Different modules running at different clock frequencies can be easily glued together. Also, since the speed independent property of asynchronous designs, modifying one part will not affect the correctness of other parts. Therefore, dynamically partial reconfiguration can be easily realized. Clock distribution is no longer a problem since the global clock signals are removed. Furthermore, unused modules in an asynchronous design could be automatically shut down to save the total power consumption. In this dissertation, the GAPLA: a GALS Programmable Logic Array architecture is presented. GALS stands for Globally Asynchronous Locally Synchronous. A GALS system consists of synchronous logic blocks operating independently under locally generated clocks and communicating with each other through handshaking asynchronous interfaces. In GAPLA, the FPGA area is divided into locally synchronous programmable logic blocks wrapped with programmable asynchronous I/O interfaces which are then connected by the routing network. Interconnect inside each synchronous block is local and fast. The long interconnects between synchronous blocks only come into picture when there are communications. The GALS design style provides different local clock domains which can be used to implement various modules in a design. The size and shape of each locally synchronous block in the GAPLA architecture are programmable so that the borders of the blocks are decided by the borders of functions instead of the architecture when implementing a design. Data communications between synchronous blocks are controlled by 2-phase handshaking signals under bundled-data delay assumption. A CAD flow of mapping designs into the GAPLA architecture is also developed. Extensive experiments are conducted to determine the optimal values for architectural parameters of the GAPLA FPGA. The area overhead of adopting the GALS style in GAPLA architecture is estimated to be small (about 19.9%). Experimental results show up to 49% performance improvement compared to the conventional FPGAs.
Dr. Ranga Vemuri (Advisor)
142 p.

Recommended Citations

Citations

  • JIA, X. (2007). GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

    APA Style (7th edition)

  • JIA, XIN. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. 2007. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281.

    MLA Style (8th edition)

  • JIA, XIN. "GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE." Doctoral dissertation, University of Cincinnati, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

    Chicago Manual of Style (17th edition)