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DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS

MAO, WUJIN
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1175553714

Abstract Details

2007, MS, University of Cincinnati, Engineering : Computer Engineering.
Dynamic circuits are widely used in today’s high-performance microprocessors for obtaining timing goals that are not possible using static CMOS circuits. Domino implementations are faster because of their smaller input capacitance, lower switching thresholds, and the availability of efficient high fan-in gates. As internal processor frequencies reach into the gigahertz range, faster circuit techniques such as clockdelayed dynamic logic was used extensively on the first CMOS microprocessor to reach 1GHz. Clock-delayed domino logic (CDDL), which can realize both inverting and non-inverting gates through the use of a self-delayed clock tree, provides any logic function to overcome such a one-way transition drawback. This thesis describes a clocking methodology of clock-delayed dynamic logic and implements a 32-bit look-ahead adder to show how the clock-delayed dynamic circuit works. CDDL has greater performance than standard domino logic, because the carefully designed clocking scheme takes pipeline advantages, by which pre-charge phase and evaluation phase are overlapped to make time borrowing. In a high-performance custom CDDL design, clock delay at each stage is fit well with the worst case delay of its previous logic level. But, due to process parameter variations and clock-tree delay, clock skews cause logic failure in CDDL. We propose a positive skew and negative skew fault model for the logic fault induced by clock skews, and analyze the fault behaviors. We take Benchmark85 circuits as experiment circuits, and design a test generation scheme. With the aid of EDA tools, we generate the test patterns to detect the clock skews faults. Experiment results show that the fault model and test generation method are correct and efficient to accomplish the goal of high fault coverage.
Dr. Wen-Ben Jone (Advisor)
109 p.
Dynamic Circuit; Domino Circuit; Clock delayed; Test

Recommended Citations

Citations

  • MAO, W. (2007). DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1175553714

    APA Style (7th edition)

  • MAO, WUJIN. DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS. 2007. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1175553714.

    MLA Style (8th edition)

  • MAO, WUJIN. "DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS." Master's thesis, University of Cincinnati, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1175553714

    Chicago Manual of Style (17th edition)

ucin1175553714
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© 2007, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.