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PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA

SWAMINATHAN, VIJAY

Abstract Details

2007, MS, University of Cincinnati, Engineering : Computer Engineering.
Most of the NoCs that exist today for FPGA use a single clock. The performance of a single clock system is limited by the delay of the slowest core whose frequency determines the frequency of operation of the entire NoC. This seems to suggest that, there exits room for improvement in using Multiple Clock NoC. Thus this work compares the performance of single and multiclock NoCs. As a part of this thesis, a router, MoCReS, has been developed. The router has its own frequency of operation and can communicate to five different cores each operating at its own frequency. In order to study the performance improvement using multiple clocks a combined experimental framework using C++ and VHDL has been developed. Various parametric experiments were considered and the results suggest that multiclock networks can result in a significant improvement in execution time in comparison to their single clock counterparts.
Dr. Karen Tomko (Advisor)
91 p.

Recommended Citations

Citations

  • SWAMINATHAN, V. (2007). PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922

    APA Style (7th edition)

  • SWAMINATHAN, VIJAY. PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA. 2007. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922.

    MLA Style (8th edition)

  • SWAMINATHAN, VIJAY. "PERFORMANCE EVALUATION OF A MULTI-CLOCK NoC ON FPGA." Master's thesis, University of Cincinnati, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1183666922

    Chicago Manual of Style (17th edition)