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Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits

BASU, SHUBHANKAR

Abstract Details

2008, PhD, University of Cincinnati, Engineering : Computer Engineering.

As semiconductor industry continues to follow Moore's Law of doubled devicecount every 18 months, it is challenged by the rising uncertainties in the manufacturing process for nanometer technologies. Manufacturing defects lead to a random variation in physical parameters like the dopant density, critical dimensions and oxide thickness. These physical defects manifest themselves as variations in device process parameters like threshold voltage and effective channel length of transistors. The randomness in process parameters affect the performance of VLSI circuits which leads to a loss in parametric yield.

Conventional design methodologies, with corner case based analysis techniques fail to predict the performance of circuits reliably in the presence of random process variations. Moreover, the analysis techniques for detection of defects in the later stages of the design cycle result in significant overhead in cost due to re-spins. In recent times, VLSI computer aided design methodologies have shifted to statistical analysis techniques for performance measurements with specific yield targets. However, the adoption of statistical techniques in commercial design flows has been limited by the complexity of their usage and the need for generating specially characterized models. This also makes them unsuitable in repeated loops during the synthesis process.

In this dissertation, we present an alternate approach to model and optimize the performance of digital and analog circuits in the presence of random process variations. Our work is targeted for a bottom-up methodology providing incremental tolerance to the circuits under the impact of random process variations. The methodologies presented, can be used to generate fast evaluating accurate macromodels to compute the bounds of performance due to the underlying variations in device parameters. The primary goal of our methodology is to capture the statistical aspects of variation in the lower levels of abstraction, while aiding deterministic analysis during the top level design optimization. We also attempt to build our solutions as a wrapper around a conventional design flow, without the requirement for special characterization. The modeling and optimization techniques are perfectly scalable across technology generations and can find practical usage during variation-tolerant synthesis of VLSI circuit performance.

Ranga Vemuri, PhD (Committee Chair)
Harold Carter, PhD (Committee Member)
Wen-Ben Jone, PhD (Committee Member)
Carla Purdy, PhD (Committee Member)
Srinivas Katkoori, PhD (Committee Member)
215 p.

Recommended Citations

Citations

  • BASU, S. (2008). Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1209682383

    APA Style (7th edition)

  • BASU, SHUBHANKAR. Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits. 2008. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1209682383.

    MLA Style (8th edition)

  • BASU, SHUBHANKAR. "Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits." Doctoral dissertation, University of Cincinnati, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1209682383

    Chicago Manual of Style (17th edition)