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Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits

Pendela Venkata Ramanjuneya, Suryanarayana
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

Abstract Details

2010, MS, University of Cincinnati, Engineering : Computer Engineering.
Much of the Semiconductor Industry’s success can be attributed to Moore’s law which states that the number of transistors on an integrated circuit would double approximately every two years. Semiconductor industry has ever since progressed from designs with a few hundred transistors to today’s complex designs incorporating millions of transistors. The current era of nanometer technologies threatens to impact the sustainability of Moore’s law with random variations in the manufacturing process impacting yield in a big way. Considerable research efforts have since been devoted to account for these variations leading to a new paradigm called Design for Manufacturing (DFM). Traditional Static Timing Analysis (STA) has given way to Statistical Static Timing Analysis (SSTA) techniques wherein the parameters considered are treated as random variables with assigned probability distribution functions. However, SSTA is still not seen as a mature flow for commercial adoption, owing to the inherent complex nature of the SSTA algorithms. In this thesis, we propose an alternate framework to STA under the presence of process variations using Interval Valued Static Timing Analysis (IVSTA). Process variations are accounted for by using a macro-modeling framework providing an efficient and fast timing analysis technique. Results on standard benchmarks show that IVSTA can predict the timing slack by a margin of 5-10% error and huge improvement of runtime compared to traditional corner based analysis. The framework involves a one-time characterization of the standard cell library and can be incorporated without much modification to the design flow. An iterative optimization framework using IVSTA engine is also presented which optimizes a routed netlist for variations at a minimum penalty of area and power.
Ranganadha Vemuri, PhD (Committee Chair)
Wen Ben Jone, PhD (Committee Member)
Carla Purdy, C, PhD (Committee Member)
95 p.
Electrical Engineering
sta; timing; process variations; ssta; static timing analysis; standard cell

Recommended Citations

Citations

  • Pendela Venkata Ramanjuneya, S. (2010). Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

    APA Style (7th edition)

  • Pendela Venkata Ramanjuneya, Suryanarayana. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. 2010. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

    MLA Style (8th edition)

  • Pendela Venkata Ramanjuneya, Suryanarayana. "Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits." Master's thesis, University of Cincinnati, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

    Chicago Manual of Style (17th edition)

ucin1268426324
645
© 2010, some rights reserved.Creative Commons License Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits by Suryanarayana Pendela Venkata Ramanjuneya is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.