Runtime Leakage Control in Deep Sub-micron CMOS Technologies

MOSFET scaling into deep sub-micro realm has resulted in significant increase in leakage power consumption. In 45nm technology generation and beyond, leakage power consumption will catch up with, and may even dominate, dynamic power consumption. This makes leakage power reduction an indispensable component for low power designs in deep sub-micro technologies. Many leakage control techniques have been introduced and studied so far. They can be characterized into two classes: runtime techniques and design-time techniques. Design-time techniques only modify the circuit and thus have limited capability of leakage reduction. On the other hand, runtime techniques tune the circuit into low-leakage mode according to the variation of circuit workload. When a circuit or a system has substantial slackness in its workload, runtime techniques can yield significant leakage saving. Hence runtime techniques, such as power gating and reverse body biasing, are widely used in industrial practices, and extensively studied in current researches as well.

Since the invention of runtime leakage control techniques (RTLC), most of they have been applied in a very crude manner. Several key questions regarding the design methodologies of RTLC remain unanswered, including how to design the optimum control policy, what is the optimum granularity of applying RTLC, and how to reduce leakage in circuit active mode. Before these questions are answered, RTLC can only be of an ad-hoc style. On top of these major questions, several other common problems in deep sub-micro technologies need to be considered before RTLC converges to a practical technique. These common problems include temperature and process variation, robustness issues in deep sub-micro technologies etc. They make the design of RTLC even more complicated and challenging.

In response to all these questions and challenges, our research aims at answering the major open questions of RTLC, tackling the practical problems in deep sub-micro technologies and finally forging a systematical solution for RTLC. To this end, this thesis studies the corresponding modeling, optimization, design methodology and design automation issues. Our whole study is driven by the following two main ideas. First, we consider that aggressive idleness exploitation is the key to achieve maximal leakage control. Second, we consider that applying RTLC in a finer manner is the key to enable aggressive idleness exploitation. Our study is based on two leakage control techniques: power gating and reserve body biasing. During our analysis, one type of RBB technique, Vth hopping, turns out to be more effective to control leakage in a finer manner. Therefore it becomes the center of our final solution.