Leakage aware designs are an indispensable part of the design and manufacturing process in today’s deep sub-micron technologies. Technology scaling continues to be a constant factor in CMOS designs, with the feature sizes of devices manufactured being scaled down below 28nm.
Starting from the 45nm technology, it has been shown that the leakage power consumption in a circuit catches up with the dynamic power consumption and continuing this trend, it has been projected that for future technologies, the leakage power consumption will even dominate the dynamic power consumption. This increasing leakage power consumption in the deep sub-micron CMOS technologies has manifested the need for more aggressive control mechanisms. The leakage control mechanisms in use today can be widely categorized into 2 categories namely, Design-Time control mechanisms and Run-Time control mechanisms. As the names suggest, Design-Time control mechanisms are incorporated into the circuit during the design phase and are not capable of dynamic control. This limits the extent of effectiveness in the leakage power reduction capability of this technique. Alternatively, Run-Time leakage control mechanisms monitor the circuit and dynamically flip it into a low power mode of working, depending upon the circuit’s workload. These techniques yield a significant power saving and a significant amount of research in low power designs today, is directed towards this technique.
The research presented by means of this thesis, is based upon a prominent run-time control mechanism known as Reverse Body Biasing. The workload of any circuit can be defined under 2 broad classifications, viz. Active mode and Standby mode. There are many robust leakage power reducing techniques that are in use today to tackle the issue during the standby mode of a circuit. It is the active mode that presents an interesting view to the problem as a whole. Scrutinizing the workload of a circuit in its active mode of working showcases that there are copious opportunities of slackness that a designer can take advantage of and utilize to construct a better leakage aware design. This is classified as Run-Time Active leakage control (RALC).
Key issues to using RALC are the optimum granularity level on which it can be applied and deciding on an efficient leakage reduction mechanism to be used with it. These issues are addressed by the technique presented as the central idea of this research, known as LITHE (Light Threshold Voltage (VTH) Hopping Technique). The idea behind LITHE is based off of a popular technique known as Threshold Voltage hopping and this is achieved by means of Adaptive Substrate Biasing. Together, this forms the core of this research. This research aims to convincingly address all the issues of the RALC as a viable solution to designing robust leakage aware designs. Aggressive exploitation of idleness during the active mode working of a circuit, fused together with the idea of LITHE, is the solution proposed towards tackling leakage power issues in deep sub-micron technologies, by means of this research. Extensive experimentation has been performed on benchmark circuits to support and verify its accuracy.