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An Express Network-on-Chip (ExNoC) Cache Architecture for Large Caches

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2011, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.

Multi-core processors with large caches have been incorporated into chip design by the continual shrinking of process technologies to fulfill performance improvement demands. A single chip with hundreds of cores is possible in the near future, but the multi-core chip is associated with ever increasing sizes of on-chip caches. Traditional bus-based cache architectures yielded long access time and significant power consumption, which does not support the demand of increasing sizes of caches. Recently proposed non-uniform cache architectures employed packet switched interconnections that were scalable for large caches. But the larger on-chip cache’s interconnection model still introduced a high network latency, which is a barrier on cache performance.

With the aim to overcome the weakness of current interconnection models on network latency, this research has proposed a novel Express Network of Chip (ExNoC) architecture for large caches, by designing a new Express Router. ExNoC model includes a new forwarding mode through an express path. It attempts to improve the bus-segmentation and Garnet interconnect model by reducing the five-stage pipeline into one clock cycle only, so as to forward the packet quicker. GEMS and Simics platforms were extended to support the performance estimation of the ExNoC system. Simulation analysis indicates that ExNoC results in the latency decrease and performance improvement by 10% to 20%. ExNoC has also been validated to be able to generate higher throughput and consume less power than current interconnection models.

Yiming Hu, PhD (Committee Chair)
Karen Davis, PhD (Committee Member)
Wen Ben Jone, PhD (Committee Member)
81 p.

Recommended Citations

Citations

  • Wu, H. (2011). An Express Network-on-Chip (ExNoC) Cache Architecture for Large Caches [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1307323725

    APA Style (7th edition)

  • Wu, Huaping. An Express Network-on-Chip (ExNoC) Cache Architecture for Large Caches. 2011. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1307323725.

    MLA Style (8th edition)

  • Wu, Huaping. "An Express Network-on-Chip (ExNoC) Cache Architecture for Large Caches." Master's thesis, University of Cincinnati, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1307323725

    Chicago Manual of Style (17th edition)