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Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects

Liu, Jianxun

Abstract Details

2011, PhD, University of Cincinnati, Engineering and Applied Science: Computer Science and Engineering.
As technology approaches deep sub-micron and clock frequency approaches Giga Hertz, the signal integrity problem of high-speed interconnects is becoming a more and more serious issue. In this work, we propose a pseudo-exhaustive testing scheme for signal integrity faults of high-speed SoC interconnects. We first validate the applicability of traditional pseudo-exhaustive testing methods to high-speed interconnect testing by validating the crosstalk locality. Base on the concept of crosstalk locality, a PE-BIST testing scheme for simple interconnect bus structures is proposed. The scheme uses a serial scan chain interface, and thus can be easily integrated with existing boundary scan architectures. Special boundary scan cells and instructions to support such integration are also discussed. The proposed PE-BIST method is then extended to arbitrary interconnect structures. With the aid of a Net Interference Graph (NIG), we can easily identify the PE-BIST test cone size and assign individual nets into PE-BIST channels. The test architecture for arbitrary interconnects is also very simple, largely reusing existing BIST components built on the chip. The hardware overhead can therefore be minimized. In order to control the test cone size for PE-BIST, shield canbe inserted into the interconnect structure to control the test time. We also present a post global routing track placement method to reduce shielding overhead. Simulation results show that the interconnect signal integrity problem can be dealt with by PE-BIST with minimum shielding overhead and reasonable test time. Finally, PE-BIST uses a parallel testing scheme and excites many aggressor nets to do the transitions which may lead to excessive power dissipation during testing. Power limit is usually considered in current SoC design, and thus the power dissipation for PE-BIST cannot be negligible. We use an efficient high level power modeling scheme to partition a PE-BIST solution into small child PE-BIST solutions so that each child PE-BIST solution can be tested within a given test power limit.
Wen Ben Jone, PhD (Committee Chair)
Chien-In Henry Chen, PhD (Committee Member)
Harold Carter, PhD (Committee Member)
Carla Purdy, PhD (Committee Member)
Ranganadha Vemuri, PhD (Committee Member)
146 p.

Recommended Citations

Citations

  • Liu, J. (2011). Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

    APA Style (7th edition)

  • Liu, Jianxun. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. 2011. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

    MLA Style (8th edition)

  • Liu, Jianxun. "Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects." Doctoral dissertation, University of Cincinnati, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

    Chicago Manual of Style (17th edition)