The revolution brought by the advancement in Integrated Circuits (IC) technology has resulted in an exponential increase in the use of smartcards and other cryptographic devices for several security-centric applications like digital signatures, identification and secure communication. This growing dependency on electronic devices for critical applications has led to increased sophistication of hardware attacks on ICs, resulting in the need for effective hardware implementation of cryptographic algorithms. Cryptographic algorithms, in spite of being mathematically secure, lose their potency when implemented in hardware due to data leakage at the hardware level through channels like power consumption, timing delay and Electromagnetic emanation. Attacks based on such leakage channels are commonly referred to as Side Channel Attacks (SCA).
Differential Power Analysis (DPA) is a sophisticated SCA method that breaks a cryptographic circuit by correlating the power consumption and the applied inputs. DPA based attacks exploit a fundamental weakness in current ASIC design methodologies (SCMOS), where the power consumption is dependent on the applied inputs. Several countermeasures have been proposed at the circuit level to prevent DPA attacks. Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) is one such countermeasure designed at Digital Design and Environments Lab at University of Cincinnati.
In this thesis, we propose a Synthesis Flow for DPA resistant circuits using Binary Decision Diagrams for the SDMLp logic style. Using the proposed design flow, we achieve an average area reduction of 35% and power saving of 30% albeit with a delay penalty of 20% compared to existing secure libraries. We also show that the maximum instantaneous current variance (security metric) is 40 times better for the proposed synthesis flow than existing synthesis techniques for other secure libraries (WDDL).