Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


ucin1335461322.pdf (7.66 MB)

ETD Abstract Container

Abstract Header

Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques

Avakian, Annie
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322

Abstract Details

2012, PhD, University of Cincinnati, Engineering and Applied Science: Computer Science and Engineering.
One of the challenges of multicore design is providing data quickly to all the processor cores running on a system. This has led to the development of architectures based on Network on Chips (NoC) due to their flexibility and scalability. In the NoC architecture, data is distributed among cache banks connected to different routers, therefore data access time varies by location. If data is accessed by two or more cores at the same time, then placing that data in the vicinity of those cores significantly improves overall access time. Recent proposals of hybrid and reconfigurable interconnect architectures try to take advantage of data locality to a certain extent by grouping processors that work on the same data set. In this dissertation, we propose migrating processor cores instead of data lines to take advantage of data locality. This is done either at static time where cores are assigned to routers before the runtime of the process with the introduction of the Reconfigurable Architecture for Multicore Systems (RAMS). In the static architecture, previous knowledge of the process characteristics is essential in determining a good configuration. We extend the idea further with the introduction of a dynamic reconfiguration entitled Dynamically Reconfigurable Multicore Architecture (DyaReMA) where cores are reassigned on the fly based on the pattern of data requests. A good test platform is essential to verify the validity of proposed architectures. We developed a complete modular hardware model that can be used to synthesize and simulate a range of architectures. The architectures proposed in literature have a homogeneous distribution of caches to routers. We propose a heterogeneous configuration of cache blocks to routers and show that the performance is significantly improved. We take this idea one step further and introduce the reconfigurable cache architecture that reassigns cache blocks to neighboring routers based on data access patterns. Hardware implementation alone cannot extract the full potential of multiocre architectures. Efficient data migration and cache coherency protocols are needed that further improve cache access time. Since data access is determined at run time, data migration has become an important part of multicore design. However, traditional data migration is expensive both due to the high cost in keeping track of all data accesses and the actual migration of data lines across multiple routers. In this dissertation, we propose a stepwise data migration scheme that improves efficiency reducing hardware cost. Data sharing introduces the need for cache coherency protocols. We propose a hybrid cache coherency protocol that combines the advantages of both broadcast and directory protocol to implement an efficient and scalable coherency method. Two coherency protocols are proposed, the first takes advantage of the characteristics of the hybrid/bus architecture. The second is targeted for NoC architectures. The proposed architectures along with data migration and cache coherency can improve data access time for L2 cache misses and help to significantly reduce the runtime of different processes in the realm of multicore architecture.
Ranganadha Vemuri, PhD (Committee Chair)
Karen Davis, PhD (Committee Member)
Wen Ben Jone, PhD (Committee Member)
Carla Purdy, PhD (Committee Member)
Karen Tomko, PhD (Committee Member)
145 p.
Computer Engineering
Multicore; Hybrid NoC; Reconfigurable Architecture; Computer Architecture; ; ;

Recommended Citations

Citations

  • Avakian, A. (2012). Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322

    APA Style (7th edition)

  • Avakian, Annie. Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques. 2012. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322.

    MLA Style (8th edition)

  • Avakian, Annie. "Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques." Doctoral dissertation, University of Cincinnati, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322

    Chicago Manual of Style (17th edition)

ucin1335461322
474
© 2012, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.