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Improving Bug Visibility using System-Level Assertions and Transactions

Barber, Kristin M
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020

Abstract Details

2013, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
The increase in complexity of hardware designs over the last several years has been unprecedented. Due to improved process technologies, the ability to integrate a number of macro components onto a single piece of silicon has enabled the phenomenon known as systems-on- chip (SoCs). Debugging such a design is cumbersome with traditional signal-level tools and the problem is exacerbated when the bug is not solely hardware-related but due to an interaction between hardware and software. As a result of increasing complexity, new design practices have been adopted to alleviate this burden. These practices rely on a high-level approach to modeling, known as transaction-level modeling (TLM). This approach can also be useful to verifi cation engineers; representing information at the transaction-level instead of the signal-level will provide faster, more intuitive detection of errors. Following this logic, the focus of this work has been to develop a method for abstracting register-transfer level (RTL) information into a transaction-level view of the system. This was accomplished by formally defining SoC behavior through fi nite state automata, creating a computational model of legal and erroneous activity throughout the system. A debug environment is also proposed which creates useful visualizations to represent system-level traffic and relationships from the results of simulation data applied to this model. Through case studies the usefulness and effectiveness of the methodology is demonstrated.
Carla Purdy, Ph.D. (Committee Chair)
Wen Ben Jone, Ph.D. (Committee Member)
George Purdy, Ph.D. (Committee Member)
79 p.
Computer Engineering
Transaction-Level Modeling TLM; Verification; Debug; System-on-Chip SoC

Recommended Citations

Citations

  • Barber, K. M. (2013). Improving Bug Visibility using System-Level Assertions and Transactions [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020

    APA Style (7th edition)

  • Barber, Kristin. Improving Bug Visibility using System-Level Assertions and Transactions. 2013. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020.

    MLA Style (8th edition)

  • Barber, Kristin. "Improving Bug Visibility using System-Level Assertions and Transactions." Master's thesis, University of Cincinnati, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020

    Chicago Manual of Style (17th edition)

ucin1377875020
532
© 2013, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.