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Arbitration Techniques for SoC Bus Interconnect with Optimized Verification Methodology

Sarpangala, Kishan

Abstract Details

2013, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
The die size of the VLSI chip has been drastically decreasing over the years while the density has been increasing exponentially with more functionality squeezed into a smaller space. The need for manufacturers to have an edge in the market and to keep up with Moore's law are the driving factors which motivated the industry to move towards SoC (System on Chip). There is more on-chip integration of different IP (intellectual property) cores, in a smaller space, with more functionality being included. This leads to problems in designing and verifying the entire design. In particular, verifying the SoC bus interconnects is difficult and presents major challenges especially with respect to time to market. One aspect of this verification involves power usage. As the complexity of the SoC increases in the communication architecture, the power consumed becomes a major concern. In terms of power use the most important component in any communication architecture is the bus interconnect and the arbiter is the major component in the bus interconnect. In this research, an effective arbiter for the bus communication which supports six priority policies will be designed. It's named Blue-Jay. Arbitration policies are applied using one of the three approaches to data multiplexing- transfer, transaction, and desired transfer length. Hence, there are total of eighteen possible arbitration schemes. To verify the functioning of our design we have developed an optimized verification methodology, based on formal methods and System Verilog. Our results show higher reliability than the commonly used AMBA arbitration scheme.
Carla Purdy, Ph.D. (Committee Chair)
Raj Bhatnagar, Ph.D. (Committee Member)
George Purdy, Ph.D. (Committee Member)
68 p.

Recommended Citations

Citations

  • Sarpangala, K. (2013). Arbitration Techniques for SoC Bus Interconnect with Optimized Verification Methodology [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384850649

    APA Style (7th edition)

  • Sarpangala, Kishan. Arbitration Techniques for SoC Bus Interconnect with Optimized Verification Methodology. 2013. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384850649.

    MLA Style (8th edition)

  • Sarpangala, Kishan. "Arbitration Techniques for SoC Bus Interconnect with Optimized Verification Methodology." Master's thesis, University of Cincinnati, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384850649

    Chicago Manual of Style (17th edition)