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Cluster Shaping: A novel optimization technique for large scale VLSI placement

Mukherjee, Tuhin
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006

Abstract Details

2014, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
The process of VLSI placement has been under constant evolution since its early days when the number of cells was ~100 to modern designs containing ~50 million cells with the process technology approaching ~7nm. We have presented a new optimization technique that increases the efficiency of existing clustering methods in placement and can place extremely large designs within a reasonable amount of time without sacrificing on the quality of solution. We have evaluated our technique based on the total wirelength (HPWL) and the timing values such as total negative slack (TNS) and worst negative slack (WNS) produced after completion of placement and routing. We have used real designs for the purpose of evaluation after converting them into the bookshelf format which is the standard format used by most academic placers today. The main concept behind our research was to extend the creation of large clusters in such a way that they could have multiple variations in shape instead of just squares. This was done to allow more flexibility in the placement of cells inside the clusters. After generation of multiple shapes an efficient selection procedure was implemented to get the best shape for a cluster from the several variations. This selection procedure consisted of assigning a shape to all the clusters and placing them in their optimal locations. Following this the cost of the placement solution was evaluated by taking into account the external and internal half perimeter wire length (HPWL) values along with the overlapping area in the design. We have used state-of-art placement tools to place the cells inside a cluster for all its variations. Synopsys DA tools were used for the purpose of evaluating our final performance. We have found from our experimental results that our shaping technique has improved the total wirelength by 8% on an average when compared to LCPlace [2] across all the benchmarks at the cost of a slight increase in runtime.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
88 p.
Engineering
VLSI placement; clustering; shaping; Timing

Recommended Citations

Citations

  • Mukherjee, T. (2014). Cluster Shaping: A novel optimization technique for large scale VLSI placement [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006

    APA Style (7th edition)

  • Mukherjee, Tuhin. Cluster Shaping: A novel optimization technique for large scale VLSI placement. 2014. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006.

    MLA Style (8th edition)

  • Mukherjee, Tuhin. "Cluster Shaping: A novel optimization technique for large scale VLSI placement." Master's thesis, University of Cincinnati, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397468006

    Chicago Manual of Style (17th edition)

ucin1397468006
388
© 2014, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.