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10592.pdf (771.12 KB)
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Abstract Header
Experiments with Hardware-based Transactional Memory in Parallel Simulation
Author Info
Hay, Joshua A
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406900877
Abstract Details
Year and Degree
2014, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
Abstract
Transactional memory is a concurrency control mechanism that dynamically determines when threads may safely execute critical sections of code. It does so by tracking memory accesses performed within a transactional region, or critical section, and detecting when memory operations conflict with other threads. Transactional memory provides the performance of fine-grained locking mechanisms with the simplicity of coarse-grained locking mechanisms. Parallel Discrete Event Simulation is a problem space that has been studied for many years, but still suffers from significant lock contention on SMP platforms. The pending event set is a crucial element to PDES, and its management is critical to simulation performance. This is especially true for optimistically synchronized PDES, such as those implementing the Time Warp protocol. Rather than prevent causality errors, events are aggressively scheduled and executed until a causality error is detected. This thesis explores the use of transactional memory as an alternative to conventional synchronization mechanisms for managing the pending event set in a time warp synchronized parallel simulator. In particular, this thesis examines the use of Intel’s hardware transactional memory, TSX, to manage shared access to the pending event set by the simulation threads. In conjunction with transactional memory, other solutions to contention are explored such as the use of multiple queues to hold the pending event set and the dynamic binding of threads to these multiple queues. For each configuration a comparison between conventional locking mechanisms and transactional memory access is performed to evaluate each within the WARPED parallel simulation kernel. In this testing, evaluation of both forms of transactional memory (HLE and RTM) implemented in the Haswell architecture were performed. The results show that RTM generally outperforms conventional locking mechanisms and that HLE provides consistently better performance than conventional locking mechanisms, up to as much as 27%.
Committee
Philip Wilsey, Ph.D. (Committee Chair)
Fred Beyette, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
Pages
74 p.
Subject Headings
Computer Engineering
Keywords
transactional memory
;
TSX
;
parallel simulation
;
parallel discrete event simulation
;
PDES
;
lock contention
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Citations
Hay, J. A. (2014).
Experiments with Hardware-based Transactional Memory in Parallel Simulation
[Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406900877
APA Style (7th edition)
Hay, Joshua.
Experiments with Hardware-based Transactional Memory in Parallel Simulation.
2014. University of Cincinnati, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406900877.
MLA Style (8th edition)
Hay, Joshua. "Experiments with Hardware-based Transactional Memory in Parallel Simulation." Master's thesis, University of Cincinnati, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406900877
Chicago Manual of Style (17th edition)
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Document number:
ucin1406900877
Download Count:
1,746
Copyright Info
© 2014, some rights reserved.
Experiments with Hardware-based Transactional Memory in Parallel Simulation by Joshua A Hay is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.