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14073.pdf (701.54 KB)
ETD Abstract Container
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A Study on Performance Binning in Error Resilient Circuits
Author Info
Nilamboor, Sanjay N
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1427798251
Abstract Details
Year and Degree
2015, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Abstract
In recent times, feature sizes of integrated circuits are shrinking and performance is on an upward trend. This has led to several interesting research ideas focussed on improving performance and error resilience, such as EDS [1]. An error resilient design has the capability to detect and recover from errors during normal operation, and can improve performance by eliminating the need for frequency guard bands and thus, paving way for higher speeds of operation. Our work tries to address the new challenges encountered while characterizing the performance of such chips. This work addresses two major aspects of performance binning in error resilient designs. Firstly, we outline a framework built using industry standard tools for performing timing analyses and performance binning of error resilient chips. Based on the throughput of a circuit employing error resilience at different frequencies, the performance binning process can be fine-tuned to improve efficiency and reduce wastage. Second, we explore the relationship between error count using path delay tests and error rate using functional benchmark programs in error resilient designs. We have performed experiments on a commercial chip using path delay tests and functional benchmark patterns. Our results demonstrate the feasibility of using delay testing to replace the time consuming functional binning process which usually is very expensive, especially for error resilient computing.
Committee
Wen-Ben Jone, Ph.D. (Committee Chair)
Carla Purdy, Ph.D. (Committee Member)
Ranganadha Vemuri, Ph.D. (Committee Member)
Pages
53 p.
Subject Headings
Electrical Engineering
Keywords
performance binning
;
atpg
;
delay test patterns
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Citations
Nilamboor, S. N. (2015).
A Study on Performance Binning in Error Resilient Circuits
[Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1427798251
APA Style (7th edition)
Nilamboor, Sanjay.
A Study on Performance Binning in Error Resilient Circuits.
2015. University of Cincinnati, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1427798251.
MLA Style (8th edition)
Nilamboor, Sanjay. "A Study on Performance Binning in Error Resilient Circuits." Master's thesis, University of Cincinnati, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1427798251
Chicago Manual of Style (17th edition)
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Document number:
ucin1427798251
Download Count:
454
Copyright Info
© 2015, some rights reserved.
A Study on Performance Binning in Error Resilient Circuits by Sanjay N Nilamboor is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.