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DPA Resistant Logic Arrays for Security Applications

Lakkaraju, Harsha Vardhan
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460

Abstract Details

2015, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Field Programmable Gate Arrays (FPGAs) are becoming an integral part of IC’s due to their increased popularity with advancements of technology and due to their various range of applications. Modern FPGAs have less power consumption, complex design size and more predictable project cycle compared to ASICs. Advancements in this technology has brought exponential growth in the use of embedded systems such as smart cards, laptops, tablets, mobile phones and other mobile technologies. This has resulted in the need for sophisticated and secured hardware implementation of cryptographic algorithms. Even though these algorithms are secured mathematically they are not effective when implemented in hardware due to side channel leakage. This provides an attacker a medium to attack the device, commonly known as side channel attacks (SCA). Differential Power Attack (DPA) is widely used medium of hardware attack. DPA attacks measure power levels at different instances of the chip and apply statistical analysis to overcome many countermeasures, such as added noise that obscures low level bit values. Measuring the power usage can identify the computational operations of the device. An analysis will reveal several bits of the crypto-key at a time; the process is repeated to eventually produce the entire key. DPA attacks are dangerous and powerful because they circumvent the hardware and software security that vendors have put in place. Because such attacks can be passive and non-invasive, it is possible for an intruder to compromise an embedded system without leaving a trace. Several countermeasures have been proposed to prevent DPA attacks at both High and Low Levels of abstraction. One such countermeasure is Secure Differential Multiplexer based Logic (SDMLp). Cellular Array based FPGA architecture has been implemented to realize the secured Logic Array in this work. In this thesis, we propose a new flow for a DPA resistant Logic Arrays using Reduced Ordered Binary Decision Diagram (ROBDD) approach using SDMLp logic style. Using the proposed design flow, an FPGA architecture is realized with one SDMLp cell (implemented as MUX) functioning as PLB. Two different architectures are proposed; the Fixed Array architecture that makes use of via and the Programmable Logic Array Architecture that is programmed using serial bit-stream inputs. In both cases, the coefficient cofactor vs. the key guesses and total number of vectors are analyzed, and the results show that the design is DPA resistant.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
83 p.
Electrical Engineering
DPA; Logic Arrays; SDMLp; FPGA; Hardware Security

Recommended Citations

Citations

  • Lakkaraju, H. V. (2015). DPA Resistant Logic Arrays for Security Applications [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460

    APA Style (7th edition)

  • Lakkaraju, Harsha Vardhan. DPA Resistant Logic Arrays for Security Applications. 2015. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460.

    MLA Style (8th edition)

  • Lakkaraju, Harsha Vardhan. "DPA Resistant Logic Arrays for Security Applications." Master's thesis, University of Cincinnati, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460

    Chicago Manual of Style (17th edition)

ucin1448037460
441
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This open access ETD is published by University of Cincinnati and OhioLINK.