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Progressive and Secure Performance Unlocking for Digital Designs

Lokare, Renuka
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479819469675449

Abstract Details

2016, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
With increasing threats such as hardware Trojans, reverse engineering and side channel attacks, hardware security has gained importance over the last decade. Design gets exposed to attacks as soon as it comes out of the design process and goes into a third-party fabrication unit. To eliminate unauthorized usage, piracy and overproduction, IP owners include additional hardware, normally in the form of key gates, to the basic functionality of an IC. The design provides logically correct output only when a correct key (or a sequence of keys) is applied. In our work, by controlling the gap between the locked and unlocked states of an IC, we have offered progressive performance unlocking of a design along with secure usage of an IC. A key comparison module authenticates the usage of an IC, uniquely identifies it and unlocks a specific mode of operation based on the user requirement. We have presented three different methods (clock enabler, ring oscillator based frequency synthesizer and progressive power unlocking) for tuning the performance and power at run-time based on the response from the key comparison module. We have proposed a secure IP owner to user interaction which not only helps the IP owner to get complete controllability over the usage of an IC but also makes the post-fabrication testing secure. We have analysed the proposed architecture on the ISCAS99 benchmark circuits and a real-time image normalization application.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
93 p.
Computer Engineering
Progressive Unlocking; Performance; Frequency Synthesizer; Response Time Tuning; Power Tuning; Digital Design Authentication

Recommended Citations

Citations

  • Lokare, R. (2016). Progressive and Secure Performance Unlocking for Digital Designs [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479819469675449

    APA Style (7th edition)

  • Lokare, Renuka. Progressive and Secure Performance Unlocking for Digital Designs. 2016. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479819469675449.

    MLA Style (8th edition)

  • Lokare, Renuka. "Progressive and Secure Performance Unlocking for Digital Designs." Master's thesis, University of Cincinnati, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479819469675449

    Chicago Manual of Style (17th edition)

ucin1479819469675449
439
© 2016, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.