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Design of DPA-Resistant Integrated Circuits

Gohil, Nikhil N
http://orcid.org/0000-0003-0308-4249
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541

Abstract Details

2017, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
During the recent past, Integrated Circuit (IC) technology has grown by leaps and bounds, with modern circuits capable of performing tasks at an extremely efficient rate. Along with the increase in usage of IC’s there is a growing need to safeguard important information that these circuits process. In addition, cryptographic devices providing security-centric functions are widely used in applications such as secure communication (encrypted messaging) and identification (digital signatures, smart- card authorization). Increased reliability on such devices for important applications has led to a multitude of attacks being developed to attack these IC’s. Although many mathematically secure algorithms have been proposed, a device is still vulnerable when implemented in hardware because of data leakage through side-channels such as power consumption, timing delay etc. This thesis focuses on Differential Power Analysis (DPA) attacks, a class of attacks that exploit data dependent power consumption of devices implemented using CMOS (Complimentary Metal-Oxide-Semiconductor) logic. Several circuit level counterme- asures have been proposed to increase resistance to DPA attacks. Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) developed in the Digital Design Environments Lab at the University of Cincinnati is one such alternative to CMOS technology. In this thesis, we test several flip-flop styles to gauge the impact of sequential elements of a circuit on DPA attacks. We then propose a design flow using the tested flip-flops and SDMLp to enable implementation of DPA resistant logic circuits. We attack AES and DES implementations using both SDMLp and CMOS and show that the SDMLp implementations are DPA resistant.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
170 p.
Engineering
Hardware Security; SDMLp; DPA; Side Channel Attacks

Recommended Citations

Citations

  • Gohil, N. N. (2017). Design of DPA-Resistant Integrated Circuits [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541

    APA Style (7th edition)

  • Gohil, Nikhil. Design of DPA-Resistant Integrated Circuits. 2017. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.

    MLA Style (8th edition)

  • Gohil, Nikhil. "Design of DPA-Resistant Integrated Circuits." Master's thesis, University of Cincinnati, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541

    Chicago Manual of Style (17th edition)

ucin1516622822794541
489
© 2017, some rights reserved.Creative Commons License Design of DPA-Resistant Integrated Circuits by Nikhil N Gohil is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.