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Logic Encryption of Sequential Circuits

Thulasi Raman, Sudheer Ram
http://orcid.org/0000-0003-2063-4564
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143

Abstract Details

2019, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
With the advent of semi conductor design industry becoming fab-less to reduce the cost incurred on maintaining the fabrication units due to the advancements in the transistor node, the IC designs are outsourced for fabrication. Miscreants in the fabri- cation industry have the potential of misusing the Intellectual Property(IP) by reverse engineering the IC and over producing the design to sell them in the black market. Hence securing the IPs has become essential. Many techniques like Logic Encryption, Split Manufacturing and Camouflaging have been developed to thwart such attacks by hiding the functionality of the circuit from the attacker. Many logic encryption techniques for combinational circuits lock the original circuit with a key scheme to prevent the circuit from working as required until the correct key value is applied. Recently, a Boolean satisfiability based attack technique was pro- posed in [1] which was able to successfully decrypt and find the correct key scheme for many logically encrypted circuits within 10 hours. Subsequently, defense methods that are resilient to the SAT attack such as SARLOCK[2], Anti-SAT[3], TTLOCK[4], etc. were proposed. Sequential logic encrypted circuits have shown to be susceptible to the sequential-SAT attack [5], and the sequential SAT attack with incremental bounded- model-checking (BMC) [6]. In this thesis we present a novel technique to encrypt a sequential circuit which is SAT attack resilient. The techniques proposed in this thesis work are: • Deep State Encryption: In this technique, a sequential circuit is encrypted by inverting the values of the primary outputs based on the occurrence of a chosen deep state in the design. • Reduced Overhead Deep State Encryption: A modification to the Deep State Encryption technique that aims at reducing the area overhead introduced by the encryption scheme is proposed. • SAT Resilient Reduced Overhead Deep State Encryption: A more secure approach which corrupts internal signals instead of primary outputs is proposed. In this technique resiliency against the SAT attack is improved by introducing a counter.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
72 p.
Computer Engineering
Logic Encryption; Sequential Circuit Logic Encryption; Sequential SAT attack; Deep State Encryption; Hardware Security; SAT Resilient Sequential Circuit Encryption

Recommended Citations

Citations

  • Thulasi Raman, S. R. (2019). Logic Encryption of Sequential Circuits [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143

    APA Style (7th edition)

  • Thulasi Raman, Sudheer Ram. Logic Encryption of Sequential Circuits. 2019. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

    MLA Style (8th edition)

  • Thulasi Raman, Sudheer Ram. "Logic Encryption of Sequential Circuits." Master's thesis, University of Cincinnati, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143

    Chicago Manual of Style (17th edition)

ucin1553251689992143
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