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Neuromorphic Architecture with Heterogeneously Integrated Short-Term and Long-Term Learning Paradigms

Bailey, Tony J
http://orcid.org/0000-0001-5904-8197
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1554217105047975

Abstract Details

2019, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
SrTiO3 (STO) based Resistive Random Access Memory (RRAM) was studied as a potential candidate device to exhibit synaptic plasticity characteristics. It had previously been studied in the context of binary-state resistive switching as well as analog, continuous-state resistance modulation. Single and crossbar-connected STO-based RRAM devices were fabricated and the single STO devices were characterized to measure their characteristics in isolation. The dominant theory of resistive state change due to the drift and diffusion of defects within the STO film was investigated using a differential voltammetry technique. The short-term synaptic plasticity was then characterized using a test battery that was able to measure repeatable potentiation and depression rates of the devices despite the time-varying nature of the resistive state in the RRAM devices. A phenomenological model was then constructed based on the potentiation and depression rates in order to model synaptic RRAM behavior in a SPICE circuit simulator. Using this model, the devices could be integrated into a spiking neural network architecture to determine their ability to learn in a realistic context. Then, the design and realization of a mixed-signal, supervised spiking neural network architecture utilizing short-term plasticity in synaptic resistive random access memory was presented. A method to perform quantized weight transfer between the short-term memory and a stable, long-term memory was then proposed, allowing the transient associated memories to be stored and used repeatedly. By integrating both memories, weight transfer and learning mechanisms onto a compact VLSI floorplan, the presented neuroprocessor architecture heterogeneously integrates short-term and long-term learning paradigms. The performance of the architecture was then tested in terms of its ability to learn and its power consumption. To test its ability to learn, a modified version of the MNIST handwritten digit set was used. The neuroprocessor was able to quickly associate the input digit with its corresponding class label, transfer those learned associations to a long-term register array, then correctly recall all digits using the long-term memory when they were presented again. The low measured operational power of 13.7mW makes such a system ideal for future integration onto embedded systems with limited available energy. Finally, the spiking neural network was applied as a heteroassociative memory and its tolerance to both input pattern noise and internal device failures was measured to be 14% and 15% respectively. The proposed neuroprocessor architecture progresses the field of neuromorphic computing by presenting clear implementation details needed to design supervised learning methods into hardware spiking neural networks. This work provides a framework to build upon to achieve more complex short-term to long-term memory interactions in the future.
Rashmi Jha, Ph.D. (Committee Chair)
Anca Ralescu, Ph.D. (Committee Member)
Ranganadha Vemuri, Ph.D. (Committee Member)
109 p.
Electrical Engineering
neuromorphic computing; spiking neural network; resistive random access memory; SrTiO3; short-term memory; synapse

Recommended Citations

Citations

  • Bailey, T. J. (2019). Neuromorphic Architecture with Heterogeneously Integrated Short-Term and Long-Term Learning Paradigms [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1554217105047975

    APA Style (7th edition)

  • Bailey, Tony. Neuromorphic Architecture with Heterogeneously Integrated Short-Term and Long-Term Learning Paradigms. 2019. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1554217105047975.

    MLA Style (8th edition)

  • Bailey, Tony. "Neuromorphic Architecture with Heterogeneously Integrated Short-Term and Long-Term Learning Paradigms." Master's thesis, University of Cincinnati, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1554217105047975

    Chicago Manual of Style (17th edition)

ucin1554217105047975
209
© 2019, some rights reserved.Creative Commons License Neuromorphic Architecture with Heterogeneously Integrated Short-Term and Long-Term Learning Paradigms by Tony J Bailey is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.