Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


40493.pdf (4.88 MB)

ETD Abstract Container

Abstract Header

SoC Security Verification Using Assertion-Based and Information Flow Tracking Techniques

Achyutha, Shanmukha Murali
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1637157958931684

Abstract Details

2021, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
A System-on-Chip (SoC) is an integrated circuit that is embedded in most electronic devices. It typically consists of a central processing unit (CPU) containing multiple cores, memory (RAM), input, output ports and a communication fabric. Due to their wide range of applications, huge demand and time to market constraints, the SoC development process (design, verification, fabrication and testing) is often distributed over various companies and countries. Throughout the SoC development process, several security vulnerabilities can come to exist. These vulnerabilities can occur due to the design bugs in the functional blocks, malicious intrusions in a 3rd party intellectual property (IP) cores and manufacturing defects in the fabrication process. When triggered during operation, vulnerabilities can lead to several undesirable outcomes, such as leaking sensitive information and denial of service. It is difficult to identify a triggered vulnerability in both pre-silicon verification and post-silicon validation. It takes many clock cycles to manifest its effect on functionality at an observable port. Hence, it is necessary to verify security policies that an SoC should enforce to mitigate vulnerabilities. These policies should be represented in formal notations and verified using static methods to ensure that the design adheres to the security policies. This thesis presents three different approaches to identify vulnerabilities in hardware (SoC) designs. The first method is to develop a library of parameterized assertions for a catalog of security policies identified from the literature. For a given SoC design, assertions are instantiated from the library with the actual signals from the architecture. There are certain security policies such as confidentiality, integrity and availability related to information flow that assertion-based methodology cannot verify directly. So, two novel Information Flow Tracking Models (IFTMs) are developed to verify such security policies. All the proposed methods in this work are compatible with static verification, dynamic verification, post-silicon validation and run-time monitoring. Security policies used in this work are represented as SystemVerilog Assertions (SVA) and verified using Cadence JasperGold formal verification tool. More than 40 security properties and 98 security assertions for six different designs are developed. Several bugs that are adversely affecting the design are identified. The demonstration shows that the proposed methods are scalable for large systems by applying them to large SoCs.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Carla Purdy (Committee Member)
Wen-Ben Jone, Ph.D. (Committee Member)
99 p.
Electrical Engineering
SoC; Assertion based verification; information flow tracking; system verilog assertions; static verification; security verification

Recommended Citations

Citations

  • Achyutha, S. M. (2021). SoC Security Verification Using Assertion-Based and Information Flow Tracking Techniques [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1637157958931684

    APA Style (7th edition)

  • Achyutha, Shanmukha Murali. SoC Security Verification Using Assertion-Based and Information Flow Tracking Techniques. 2021. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1637157958931684.

    MLA Style (8th edition)

  • Achyutha, Shanmukha Murali. "SoC Security Verification Using Assertion-Based and Information Flow Tracking Techniques." Master's thesis, University of Cincinnati, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1637157958931684

    Chicago Manual of Style (17th edition)

ucin1637157958931684
27
© 2021, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.