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DESIGN OF HEURISTICS FOR CONGESTION CONTROL IN 3-DIMENSIONAL ROUTING FOR MULTI-CHIP MODULES

THELAPURATH, SHRINATH
http://rave.ohiolink.edu/etdc/view?acc_num=ucin981478715

Abstract Details

2001, MS, University of Cincinnati, Engineering : Computer Engineering.
This thesis presents the design and implementation of a fast greedy heuristic router for multichip module designs. The router divides the design in to regions and attempts to topologically lay down the wires. There are some heuristics which guide this process such that the subsequent steps are facilitated. Once the wires are laid down, the router then aims to reduce congestion of wires which is identified as the parameter which when controlled gives effcient routing results. The heuristics are targeted towards reducing the number of layers taken, keeping the wirelength as close to optimal as possible without using any global routing information, and facilitating fast eneration of individual routes. Nets are routed one by one, but as the nets are broken down in to smaller pieces which lie in the region being routed, and because there are many such net segments, routing results do not show dependence on the net ordering. The router works by processing individual regions and since the regions can be processed in any order, any non-adjacent region can be processed in parallel. It is observed that though global optimization is not done, the wirelength and number of vias obtained is very close to those obtained by other routers developed in academia, when run on industry level benchmarks. The router also shows fast execution times as expected of any greedy router. If incremental changes are made to the design, the particular region can be rerouted and as this is done fast, the router is suitable for incremental routing.
Dr. Dinesh Bhatia (Advisor)
79 p.
Computer Science
congestion removal techniques; memory utilization; speed of execution; region splitting; greedy heuristic approach

Recommended Citations

Citations

  • THELAPURATH, S. (2001). DESIGN OF HEURISTICS FOR CONGESTION CONTROL IN 3-DIMENSIONAL ROUTING FOR MULTI-CHIP MODULES [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin981478715

    APA Style (7th edition)

  • THELAPURATH, SHRINATH. DESIGN OF HEURISTICS FOR CONGESTION CONTROL IN 3-DIMENSIONAL ROUTING FOR MULTI-CHIP MODULES. 2001. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin981478715.

    MLA Style (8th edition)

  • THELAPURATH, SHRINATH. "DESIGN OF HEURISTICS FOR CONGESTION CONTROL IN 3-DIMENSIONAL ROUTING FOR MULTI-CHIP MODULES." Master's thesis, University of Cincinnati, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin981478715

    Chicago Manual of Style (17th edition)

ucin981478715
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© 2001, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.