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INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS

BHALGAT, ASHISH ZUMBARLAL
http://rave.ohiolink.edu/etdc/view?acc_num=ucin982261963

Abstract Details

2001, MS, University of Cincinnati, Engineering : Computer Engineering.
Modern computers are taking increasing advantage of the instruction-level parallelism (ILP) available in application programs. Advances in the architectural design of the Application Specific Instruction Core (ASIC) embedded processors often result in complex and irregular processor architectures. Most of the modern embedded processors use both pipelining & multiple instruction issue techniques in order to execute the instructions in parallel and run the application programs much faster. Performance of such Very Long Instruction Word (VLIW) architectures is mainly dependent on the capability of the compiler to detect and exploit the ILP. To take the advantage of the inherently available parallelism in the code, instruction are reordered so that the length of code schedule can be reduced. Thus, code motion of instructions may minimize the overall cycle count resulting in better code execution efficiency. However, code reordering is often constrained by the dependencies among the instructions due to the control and data flow inherent in the code. Further, compile time instruction scheduling for such irregular architectures is a challenging problem due to the architectural constraints imposed on the restructuring of instructions. In this thesis, we present a framework to restructure the instructions to exploit the ILP through the parallel instructions available in the Instruction Set Architecture (ISA) of our EPIC VLIW Digital Signal Processor. We focus on the memory access instructions, loads and stores, and optimize the schedule to hide the load/store instruction latency.
Santosh Pande (Advisor)
72 p.
DSP; VLIW; Dynamic Scheduling; Just In Time (JTT) Scheduling; Compiler Optimization

Recommended Citations

Citations

  • BHALGAT, A. Z. (2001). INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982261963

    APA Style (7th edition)

  • BHALGAT, ASHISH. INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS. 2001. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin982261963.

    MLA Style (8th edition)

  • BHALGAT, ASHISH. "INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS." Master's thesis, University of Cincinnati, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982261963

    Chicago Manual of Style (17th edition)

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© 2001, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.