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On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test

Poling, Brian
http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023

Abstract Details

2007, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
Poling, Brian S. M.S. Egr., Department of Electrical Engineering, Wright State University, 2007. On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In Self-Test. Built-In Self-Test (BIST) is a method of designing and creating an electronic chip or an electronic system that can self test for correct functionality and ensure no manufacturing defects. The reason for analog BIST is the testing of analog parts of analog and mixed-signal ICs is a costly process that traditionally requires the use of expensive high-end automatic test equipment. Due to the nature of the testing and length of the testing process, an efficient analog BIST scheme is in high demand for the ever increasing complexity of analog and mixed-signal circuits. This thesis presents a BIST scheme for generation and response waveform extraction that allows the detection of a faulty circuit design. Along with the detection, an approach to test high speed analog and mixed-signal circuits with test signals upwards of 1GHz is presented. A practical application is to test analog or mixed-signal IC that has a wide bandwidth ADC in its front-end. The BIST scheme includes a method to store the test signal and generate it for the circuit to be tested along with a way to extract the response test signal from multiple test points and allow fault detection. Along with this research, a stepping stone is implemented for analog modeling using MATLAB for accuracy and speed of circuit simulations. The problems associated with the BIST scheme and analog modeling is discussed, along with recommendations.
Henry Chen (Advisor)
131 p.
Buffer Design; BIST; ANALOG; 1GHz; DAC; ADC; Final Buffer

Recommended Citations

Citations

  • Poling, B. (2007). On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023

    APA Style (7th edition)

  • Poling, Brian. On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test. 2007. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023.

    MLA Style (8th edition)

  • Poling, Brian. "On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test." Master's thesis, Wright State University, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023

    Chicago Manual of Style (17th edition)

wright1190050023
935
© 2007, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.