A digital single sideband modulator (DSSM) for a digital radio frequency memory (DRFM) was designed and implemented in a commercial 90-nm radiation-hardened-by-design (RHBD) structured ASIC by Thomas Pemberton in cite{Pemberton}. This thesis synthesized the same DSSM structure in a non-hardened 90-nm commercial process and compared the synthesis results of the two for power, delay, and area. The number of I/O bits and taps in cite{Pemberton} and this thesis were purposely made high to create a large target for radiation testing. As should be expected, the RHBD DSSM reported greater power and area. However, the RHBD power models were only estimates.
This thesis also showed the costs and benefits for varying bit widths, number of filter taps, and ROM sizes in the DSSM, synthesized at a typical characterization corner. One of the designs was also synthesized at two more characterization corners. Finally, another design variation was tested with extra piping in the Hilbert filter. All of these circuits were measured for power, timing, critical path, area, and spur-free dynamic range (SFDR).
Chip area was found to be solely dependent on the number of I/O pads and thus went up with greater I/O bit widths. Greater I/O bit widths and number of taps also led to more cell area and power consumption. The 16-bit/153-tap and 24-bit/101-tap typical-corner DSSM's and the 16-bit/101-tap slow-corner DSSM could not meet the synthesis target of 100 MHz. Setup circuitry for the ROM address became the critical path for some of the designs partly due to the fact that the address was set up on the falling edge of the clock but loaded on the rising edge. Increasing I/O bit widths and the number of filter taps improved frequency response and SFDR. Finally, increasing ROM size increased maximum SFDR for a select range of input frequencies. For SFDR, the predominant spur was the suppressed sideband, which was poorly suppressed.