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wright1302048032.pdf (1.71 MB)
ETD Abstract Container
Abstract Header
Circuit Techniques on Improving Timing and Noise in Dynamic CMOS
Author Info
Vaidyanadeswaran, Arvind
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=wright1302048032
Abstract Details
Year and Degree
2011, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
Abstract
Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are inherently less noise tolerant than Static CMOS circuits. This problem becomes more severe with aggressive technology scaling into nanometer process, particularly caused by the charge sharing, the sub-threshold leakage current, the power rail noise and the crosstalk noise. In this thesis, circuit techniques on improving both timing and noise of Dynamic CMOS are presented. A comparison with previous reported work is also presented. Simulations proved that the proposed circuit techniques can achieve a high level of timing optimization and noise tolerance. Finally, the effect of manufacturing process variations is taken into simulation to verify overall performance variation in delay uncertainty
Committee
Henry Chen, PhD (Advisor)
Marian Kazimierczuk, PhD (Committee Member)
Yan Zhuang, PhD (Committee Member)
Pages
61 p.
Subject Headings
Electrical Engineering
Keywords
CMOS
;
circuit techniques
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Citations
Vaidyanadeswaran, A. (2011).
Circuit Techniques on Improving Timing and Noise in Dynamic CMOS
[Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1302048032
APA Style (7th edition)
Vaidyanadeswaran, Arvind.
Circuit Techniques on Improving Timing and Noise in Dynamic CMOS.
2011. Wright State University, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=wright1302048032.
MLA Style (8th edition)
Vaidyanadeswaran, Arvind. "Circuit Techniques on Improving Timing and Noise in Dynamic CMOS." Master's thesis, Wright State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1302048032
Chicago Manual of Style (17th edition)
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Document number:
wright1302048032
Download Count:
605
Copyright Info
© 2011, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.