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Design of a Low Power and Area Efficient Digital Down Converter and SINC Filter in CMOS 90-nm Technology

Billman, Steven John

Abstract Details

2011, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
A digital down converter (DDC) typically receives a digital input that has been generated by an analog to digital converter (ADC) operating at intermediate frequency (IF) in an RF receiver chain. The function of the DDC is to down convert the IF signal to baseband in phase (I) and quadrature (Q) signals and is a very important component in wireless receivers. A Digital Down Converter (DDC) is developed based on square wave local oscillators facilitating a multiplier-less implementation with no constraints on the sampling frequency. The DDC includes a pseudo multi-rate SINC low pass filter which exhibits better performance compared to the standard multi-stage SINC filter. The pseudo multi-rate SINC filter can be implemented with a unique cascaded integrator comb (CIC) filter to obtain the same improved performance. A 90nm CMOS design takes 8 bit inputs centered at 25 MHz with a bandwidth of 30 MHz and is clocked at 400MHz. The design demonstrates a flexible, very low power/size DDC architecture for single chip digital receiver applications. The layout area is 333.485um x 617.6um and the power consumption is 12.54mW when clocked at 400MHz.
Saiyu Ren, PhD (Advisor)
Raymond Siferd, PhD (Committee Member)
Stephen Hary, PhD (Committee Member)
96 p.

Recommended Citations

Citations

  • Billman, S. J. (2011). Design of a Low Power and Area Efficient Digital Down Converter and SINC Filter in CMOS 90-nm Technology [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1307746437

    APA Style (7th edition)

  • Billman, Steven. Design of a Low Power and Area Efficient Digital Down Converter and SINC Filter in CMOS 90-nm Technology. 2011. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1307746437.

    MLA Style (8th edition)

  • Billman, Steven. "Design of a Low Power and Area Efficient Digital Down Converter and SINC Filter in CMOS 90-nm Technology." Master's thesis, Wright State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1307746437

    Chicago Manual of Style (17th edition)