As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) technologies, two problems become dominant: substrate noise caused by digital clocks interfering with highly sensitive analog and radio frequency (RF) components and parametric variations that can cause circuit delays to vary in excess of 35%. Clockless logic (or asynchronous) circuits address both of these issues and more. Clockless, asynchronous circuits are by nature delay-insensitive making them immune to parametric variations. Even more important is the processing characteristics of clockless asynchronous circuits, which eliminate highly intricate clock signals that cause large power spikes every time they switch. Consequently, asynchronous design is becoming more and more attractive for low-noise, low-power applications.
In a clock free environment, energy is a more relevant metric than power. In this work, we present algorithms that attempt to minimize the energy in asynchronous integrated circuits. Our techniques are based on voltage scaling (VS) and gate sizing (GS). On average, performing a two-stage energy reduction with VS followed by GS results in 26% energy reduction.