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Thesis_2014_Vijay.pdf (3.17 MB)

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16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies

Boppana, Naga Venkata Vijaya Krishna
http://orcid.org/0000-0001-7331-317X
http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477

Abstract Details

2014, Master of Science in Engineering (MSEgr), Wright State University, Electrical Engineering.
High speed, low power, and area efficient adders and comparators continue to play a key role in hardware implementation of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This thesis demonstrates a unique custom designed 16-bit adder in 250-nm CMOS technology to obtain fast and power/area efficient features by combining CPL and CS logic. Comparing the results obtained for proposed 16-bit Linear CPL/CS adder with the BEC (Binary Excess-1 Code) based low power SQRT-CS adder, the delay is reduced by approximately one thirds, power is reduced by 19.2%, and the number of transistors is reduced by 23.4%. Also, new tree-based 64-bit static and dynamic digital comparators are presented in this thesis to perform high speed and low power operations. This tree-based architecture combines a new approach of designing dynamic comparator using a low duty cycle clock to reduce the short circuit power consumption in pre-charge (or pre-discharge) mode. This work also introduces a new sizing strategy and load balancing techniques to improve self-pipelining tendency of a tree based design. A resource sharing technique is also integrated in both static and dynamic comparator designs. At 1.2V power supply in CMOS 90nm technology, worst path delay and worst power are 374ps and 822µW, respectively for low cost static design with 1244 (768+476) transistors in total. 768 transistors are used for resource sharing. The proposed full and partially dynamic designs show superior power efficiency compared to recent state of art designs. The worst power consumptions at 5GHz and 25% (50ps) duty cycle clock for the 64-bit full and partially dynamic comparator designs are 5.00mW and 2.78mW, respectively. 769 (320+449) transistors includes 320 transistors for resource sharing, and 1217 (768+449) includes 768 transistors for resource sharing for full and partial dynamic comparators, respectively.
Saiyu Ren, Ph.D (Advisor)
Raymond E. Siferd, Ph.D (Committee Member)
John M. Emmert, Ph.D (Committee Member)
Robert E. W. Fyffe, Ph.D (Other)
75 p.
Electrical Engineering; Nanotechnology
electrical engineering; nanotechnology

Recommended Citations

Citations

  • Boppana, N. V. V. K. (2014). 16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477

    APA Style (7th edition)

  • Boppana, Naga Venkata Vijaya Krishna. 16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies. 2014. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477.

    MLA Style (8th edition)

  • Boppana, Naga Venkata Vijaya Krishna. "16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies." Master's thesis, Wright State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477

    Chicago Manual of Style (17th edition)

wright1420674477
2,193
© 2014, some rights reserved.Creative Commons License 16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies by Naga Venkata Vijaya Krishna Boppana is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.