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Abstract Header

Implementation of Logic Fault Tolerance on a Dynamically Reconfigurable FPGA

Jayarama, Kiran
http://rave.ohiolink.edu/etdc/view?acc_num=wright1484515146085997

Abstract Details

2016, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Relative to integrated circuit (IC) systems, on-chip fault detection entails determi- nation of whether or not a fault exists. The cause of the fault could be some faulty logic resource or some faulty interconnect (wiring) resource, but typically, fault detection only determines if a fault exists, not what exactly is faulty. Beyond pure fault detection some work has been done relative to on-chip fault analysis to fur- ther determine not only if a fault exists, but exactly what is faulty. Even less work has been done to actually tolerate faulty resources once they have been found. For this work, we take advantage of previous work (ROVING STARS) that detects on-chip faults and analyzes those faults to determine exactly what is faulty. We developed, tested and demonstrated an on-chip technique that takes advantage of dynamic partially reconfigurable field programmable gate arrays (FPGAs) to automatically reconfigure the FPGA for tolerating logic faults.
John Marty Emmert, Ph.D. (Advisor)
Saiyu Ren, Ph.D. (Committee Member)
Raymond Siferd, Ph.D. (Committee Member)
52 p.
Electrical Engineering
Reconfigurable FPGA; Fault Tolerance; Dynamically Reconfigurable FPGA

Recommended Citations

Citations

  • Jayarama, K. (2016). Implementation of Logic Fault Tolerance on a Dynamically Reconfigurable FPGA [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484515146085997

    APA Style (7th edition)

  • Jayarama, Kiran. Implementation of Logic Fault Tolerance on a Dynamically Reconfigurable FPGA. 2016. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1484515146085997.

    MLA Style (8th edition)

  • Jayarama, Kiran. "Implementation of Logic Fault Tolerance on a Dynamically Reconfigurable FPGA." Master's thesis, Wright State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484515146085997

    Chicago Manual of Style (17th edition)

wright1484515146085997
752
© 2016, some rights reserved.Creative Commons License Implementation of Logic Fault Tolerance on a Dynamically Reconfigurable FPGA by Kiran Jayarama is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.