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Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS

Kotti, Vivek
http://orcid.org/0000-0002-9065-685X
http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087

Abstract Details

2017, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Analog to Digital Converters bridge the gap between physical world and digital signal processing. Most times analog signals received from the real world needs to be amplified and converted to digital to impart various signal enhancements to the received signal. The digital signal is much suitable to operate on with less noise and well defined logic levels when compared to continuously varying analog signal. Communication systems demand ever-increasing bandwidth which unfortunately has been a huge limitation for present day ADCs. Hence, an architecture which combines the accuracy of a SAR -ADC with the concept of pipelining to increase the bandwidth can be a great solution to achieve high sampling frequency (GHz) and broad bandwidth. The 8- bit SAP ADC implemented in this thesis using 90nm COMS technology achieves a sampling rate of 1GHz with input frequencies up to 125MHz
Saiyu Ren, Ph.D. (Advisor)
Raymond Siferd, Ph.D. (Committee Member)
Marian Kazimierczk, Ph.D. (Committee Member)
61 p.
Electrical Engineering
electrical engineering

Recommended Citations

Citations

  • Kotti, V. (2017). Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087

    APA Style (7th edition)

  • Kotti, Vivek. Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS . 2017. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087.

    MLA Style (8th edition)

  • Kotti, Vivek. "Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS ." Master's thesis, Wright State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087

    Chicago Manual of Style (17th edition)

wright1503596547020087
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© 2017, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.