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Layout Implementation of A 10-Bit 1.2 GS/s Digital-to-Analog Converter In 90nm CMOS

Chunchu, Vinay Kumar
http://rave.ohiolink.edu/etdc/view?acc_num=wright1515626468169571

Abstract Details

2017, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Digital-to-analog converters are the interface circuits between digital and analog domains. They are used in data communication applications and different sorts of applications where transformation amongst digital and analog signals is needed. High-speed data converters are needed to match the bandwidth demands of the present-day communication systems. This thesis presents the layout implementation of a 10-bit current steering DAC with a sampling rate of about 1.2 GS/s using CMOS 90 nm technology. Current steering DAC topology is used in high-speed applications. The DAC in this thesis is designed using a segmented architecture in which 4 LSB current cells are binary weighted and 6 MSB current cells are thermometer encoded. The issues with the mixed signal layout were discussed. The schematic design does not consider the effect of parasitic resistance and capacitance whereas the layout does. The performance of the schematic and layout designs of the sub-circuits was compared. Post layout simulations of the implemented current steering DAC were performed in Cadence with 1.2 GHz clock and 55.07 MHz input signal. The simulations show that the DAC is functional and comparisons between the layout and schematic were presented.
Saiyu Ren, Ph.D. (Advisor)
Raymond E. Siferd, Ph.D. (Committee Member)
Marian K. Kazimierczuk, Ph.D. (Committee Member)
Yan Zhuang, Ph.D. (Committee Member)
72 p.
Electrical Engineering
electrical engineering

Recommended Citations

Citations

  • Chunchu, V. K. (2017). Layout Implementation of A 10-Bit 1.2 GS/s Digital-to-Analog Converter In 90nm CMOS [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1515626468169571

    APA Style (7th edition)

  • Chunchu, Vinay Kumar. Layout Implementation of A 10-Bit 1.2 GS/s Digital-to-Analog Converter In 90nm CMOS. 2017. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1515626468169571.

    MLA Style (8th edition)

  • Chunchu, Vinay Kumar. "Layout Implementation of A 10-Bit 1.2 GS/s Digital-to-Analog Converter In 90nm CMOS." Master's thesis, Wright State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1515626468169571

    Chicago Manual of Style (17th edition)

wright1515626468169571
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© 2017, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.