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Final_Thesis - Akshay_M_R.pdf (1.01 MB)

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High-Speed Testable Radix-2 N-Bit Signed-Digit Adder

Manjuladevi Rajendraprasad, Akshay
http://orcid.org/0000-0002-2796-1915
http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539

Abstract Details

2019, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Signed-digit representation has been used to perform fast binary addition by eliminating the dependant carry chains. In this thesis, a high-speed radix-2 signed-digit architecture is first presented, which is easily expandable to 8-bit, 16-bit, 32-bit, and 64-bit signed-digit adder. The architecture mainly consists of two digital components: 1) 2s complement adder, and 2) redundant binary to 2s complement converter. The 2s complement adder adds two input operands and gives the sum resulting in a signed-digit format. The redundant binary to 2s complement converter converts the redundant binary format to the 2s complement format output. Next, by using a blend of software and custom design optimization, the 2s complement adder, the redundant binary to 2s complement converter, and the N-bit signed-digit adder (for N= 8, 16, 32, 64) are all 100% testable.
Henry Chen, Ph.D. (Advisor)
Ray Siferd, Ph.D. (Committee Member)
Marian K. Kazimierczuk, Ph.D. (Committee Member)
63 p.
Electrical Engineering
Signed-digit; radix-2 signed-digit; signed-digit adder; binary addition; 2s complement adder; redundant binary to 2s complement converter

Recommended Citations

Citations

  • Manjuladevi Rajendraprasad, A. (2019). High-Speed Testable Radix-2 N-Bit Signed-Digit Adder [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539

    APA Style (7th edition)

  • Manjuladevi Rajendraprasad, Akshay. High-Speed Testable Radix-2 N-Bit Signed-Digit Adder. 2019. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539.

    MLA Style (8th edition)

  • Manjuladevi Rajendraprasad, Akshay. "High-Speed Testable Radix-2 N-Bit Signed-Digit Adder." Master's thesis, Wright State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539

    Chicago Manual of Style (17th edition)

wright1566226346050539
501
© 2019, all rights reserved.
This open access ETD is published by Wright State University and OhioLINK.