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A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing

Allwin, Priscilla Sharon
http://orcid.org/0000-0003-2921-8022
http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305

Abstract Details

2019, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
Multimedia systems play an essential part in our daily lives and have drastically improved the quality of life over time. Multimedia devices like cellphones, radios, televisions, and computers require low-area and low-power reconfigurable adders to process greedy computation algorithms for the real-time audio/video signal and image processing such as discrete cosine transform, inverse discrete cosine transform, and fast Fourier transform, etc. In this thesis, a novel 64-bit reconfigurable adder is proposed and implemented to reduce the area and power consumption. This adder can be run-time reconfigured to different reconfigurable word lengths, i.e., one 64- bit, two 32-bits, four 16-bits or eight 8-bits addition, depending on the partition signal command. A Carry Select Modified Tree (CSMT) based adder is used in the reconfigurable adder to reduce the area by 22 % and the power consumption by 47 % when compared to the conventional design. The proposed adder, implemented in 180 nm CMOS technology at 1.8-volt supply, has a worst-case Delay of 20.67 nanoseconds with an overall area of 36,417 μm² and power consumption of 447.93 μW
Henry Chen, Ph.D. (Advisor)
Saiyu Ren, Ph.D. (Committee Member)
Raymond E. Siferd, Ph.D. (Committee Member)
63 p.
Electrical Engineering
Data Path; Media Signal Processing; Reconfigurable Adders; Carry Select Modified Tree Adder

Recommended Citations

Citations

  • Allwin, P. S. (2019). A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305

    APA Style (7th edition)

  • Allwin, Priscilla. A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing. 2019. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305.

    MLA Style (8th edition)

  • Allwin, Priscilla. "A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing." Master's thesis, Wright State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305

    Chicago Manual of Style (17th edition)

wright1566754181334305
316
© 2019, some rights reserved.Creative Commons License A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing by Priscilla Sharon Allwin is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.