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Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology

Vissamsetty, Kanchan
http://rave.ohiolink.edu/etdc/view?acc_num=wright1630106063345183

Abstract Details

2021, Master of Science in Electrical Engineering (MSEE), Wright State University, Electrical Engineering.
As feature size is scaling down, dynamic power consumption reduces but static power consumption increases. Due to the increase of static power, leakage currents as a source, the information can be exploited successfully as a side-channel to recover the secrets of the cryptographic implementations. An attacker who has access to the hardware fabrication can insert a Trojan to the design to steal or alter information. In this thesis, a post-fab static voltage variation/detection technique is developed to detect the potential fabrication process Trojan insertion. The technique is, dividing the designed circuit into N equal segments, where each segment would have same leakage current under certain input patterns. One-ohm resistor is embedded between each segment network to ground path to convert leakage current to voltage. Voltage drop on the one-ohm resistor is measured post-fab to identify the authentic of the design mathematically and statistically by comparing all the segment measure data. 250 Monte Carlo simulation results show that the minimum Trojan is 0.0868% of the host circuit size with 100% detection probability.
Saiyu Ren, Ph.D. (Advisor)
Ray Siferd, Ph.D. (Committee Member)
Marian K. Kazimierczuk, Ph.D. (Committee Member)
74 p.
Electrical Engineering
hardware security; side channel; CMOS technology; Trojan detection

Recommended Citations

Citations

  • Vissamsetty, K. (2021). Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology [Master's thesis, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1630106063345183

    APA Style (7th edition)

  • Vissamsetty, Kanchan. Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology. 2021. Wright State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1630106063345183.

    MLA Style (8th edition)

  • Vissamsetty, Kanchan. "Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology." Master's thesis, Wright State University, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1630106063345183

    Chicago Manual of Style (17th edition)

wright1630106063345183
254
© 2021, some rights reserved.Creative Commons License Hardware Security and Side Channel Power Analysis for 16X16 Booth Multiplier in 65nm CMOS Technology by Kanchan Vissamsetty is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.