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Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

Zhang, Xiaomeng
http://orcid.org/0000-0001-5782-6055
http://rave.ohiolink.edu/etdc/view?acc_num=wright1643035445595418

Abstract Details

2022, Doctor of Philosophy (PhD), Wright State University, Electrical Engineering.
5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz.
Saiyu Ren, Ph.D. (Advisor)
Raymond E. Siferd, Ph.D. (Committee Member)
Yan Zhuang, Ph.D. (Committee Member)
Henry Chen, Ph.D. (Committee Member)
Marian K. Kazimierczuk, Ph.D. (Committee Member)
130 p.
Electrical Engineering
Phase shifter; Phase-domain digital PLL; PLL; 90-degree phase shifter; Calibration system; 5G

Recommended Citations

Citations

  • Zhang, X. (2022). Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications [Doctoral dissertation, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1643035445595418

    APA Style (7th edition)

  • Zhang, Xiaomeng. Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications. 2022. Wright State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1643035445595418.

    MLA Style (8th edition)

  • Zhang, Xiaomeng. "Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications." Doctoral dissertation, Wright State University, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=wright1643035445595418

    Chicago Manual of Style (17th edition)

wright1643035445595418
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© 2022, some rights reserved.Creative Commons License Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications by Xiaomeng Zhang is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.