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An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology

Munugala, Anvesh

Abstract Details

2018, Master of Science in Engineering, Youngstown State University, Department of Electrical and Computer Engineering.
The aim of this project is to design a small FPGA chip with 0.5 µ methodology. The standard cell-based ASIC implementation of 8-bit serial communication module using the Synopsys EAD tools is presented. The design was also fabricated by MOSIS. By using Synopsys Design Compiler, IC compiler and Custom Compiler flow, simulation results are presented with the verification of logical and physical design features such as area, timing, any hold violations, Design Rule Check (DRC). This design methodology describes the RTL to GDS implementation of 8-bit serial communication module using Synopsys tools. The proposed design has 10 Input and Output ports, 54 registers. The design has passed all the Timing checks, Functional verification, Metal density requirements, Physical design verification, Layout vs Schematic. The baud rate generator which mimics a clock signal is supplied to the receiver module. The desired baud rate can be chosen from the baud rate generator. The serial communication protocol can be used for reading a sensor’s bit stream data.
Frank Li, PhD (Advisor)
Eric MacDonald, PhD (Advisor)
Jalal Jalali, PhD (Committee Member)
75 p.

Recommended Citations

Citations

  • Munugala, A. (2018). An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology [Master's thesis, Youngstown State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399

    APA Style (7th edition)

  • Munugala, Anvesh. An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology. 2018. Youngstown State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399.

    MLA Style (8th edition)

  • Munugala, Anvesh. "An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology." Master's thesis, Youngstown State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399

    Chicago Manual of Style (17th edition)