Layered Manufacturing machines use the Stereolithography (STL) file to build parts by various Rapid Prototyping and Rapid Manufacturing processes. When a curved surface is converted from a CAD file to STL, it results in a geometrical distortion. Parts manufactured with this file, may not satisfy Geometric Dimensioning and Tolerance (GD and T) requirements due to approximated geometry. Current algorithms built in CAD packages have export options to globally reduce this distortion which leads to an increase in the file size and pre-processing time.
An innovative approach to locally reduce the GD and T errors at feature level is presented in this research. The algorithm presented in this work performs virtual manufacturing, inspection and STL modification iteratively, on a feature STL file until the specified GD and T parameter on the feature surface is satisfied. The approach, termed as the Vertex Translation Algorithm (VTA), compares STL surface to the NURBS design surface, while computing the chord error at multiple points on the STL facets. The point on design surface with largest chord error is selected as the new vertex and new facets are generated. The algorithm ensures selective and localized modification of STL file, and satisfies the GD and T requirements. Facets corresponding to a feature surface are isolated from the main part STL with a novel Facet Isolation Algorithm. The modified feature STL is stitched back to the main STL after modification. This algorithm ensures selective and localized STL modification, to produce a part with required GD and T specifications. In this research chord error, profile error, cylindricity and surface roughness have been evaluated on test parts and an improvement in values has been observed with each modification.